Cryogenic DRIE Processes for High-Precision Silicon Etching in MEMS Applications

Abstract

Cryogenic deep reactive ion etching (Cryo DRIE) of silicon has become an enticing but challenging process utilized in front-end fabrication for the semiconductor industry. This method, compared to the Bosch process, yields vertical etch profiles with smoother sidewalls not subjected to scalloping, which are desired for many microelectromechanical systems (MEMS) applications. Smoother sidewalls enhance electrical contact by ensuring more conformal and uniform sidewall coverage, thereby increasing the effective contact area without altering contact dimensions. The versatility of the Cryo DRIE process allows for customization of the etch profiles by adjusting key process parameters such as table temperature, O2 percentage of the total gas flow rate (O2 + SF6), RF bias power, and process pressure. In this work, we undertake a comprehensive study of the effects of Cryo DRIE process parameters on the trench profiles in the structures used to define cantilevers in MEMS devices. Experiments were performed with an Oxford PlasmaPro 100 Estrelas ICP-RIE system using positive photoresist SPR-955 as a mask material. Our findings demonstrate significant influences on the sidewall angle, etch rate, and trench shape due to these parameter modifications. Varying the table temperature between -80°C and -120°C under a constant process pressure of 10 mTorr changes the etch rate from 3 to 4 µm/min, while sidewall angle changes by ~2°, from positive (<90° relative to the Si surface) to negative (>90° relative to the Si surface) tapering. Altering the O2 flow rate with constant SF6 flow results in a notable 10° shift in sidewall tapering. Furthermore, SPR-955 photoresist masks provide selectivity of 46:1 with respect to Si and facilitates the fabrication of MEMS devices with precise dimension control ranging from 1 to 100 µm for etching depths up to 42 µm using Cryo DRIE. Understanding the influence of each parameter is crucial for optimizing MEMS device fabrication.