Design of lightweight memory protection solution based on RISC-V processor

Abstract

With the rapid advancement of modern processor technologies, the potential threat to processor memory security from external devices necessitates robust memory protection mechanisms. To ensure the stability and security of processors, Input-Output (IO) physical memory protection mechanisms are commonly employed to prevent unauthorized access to processor memory. However, the redundancy in the mapping relationships between modules in traditional IO physical memory protection mechanisms leads to an increase in processor runtime. This paper, focusing on RISC-V processors, presents an efficient memory protection scheme, named L-OPT, by investigating traditional IO physical memory protection approaches. L-OPT optimizes the mapping relationships between internal modules in conventional memory protection schemes. In comparison with the unoptimized state of the processor in memory testing scenarios, L-OPT demonstrates a 112% efficiency improvement, validating its effectiveness in enhancing processor runtime efficiency.