Design of a hysteresis comparator with temperature compensation

Abstract

Utilizing 0.18μm CMOS process, a hysteresis comparator with temperature compensation has been devised. A compensating current is generated through two NMOS transistors operating in the linear region, thereby mitigating the temperature-dependent coefficients in the hysteresis voltage expression to achieve heightened precision in hysteresis voltage. The model is constructed using Cadence software, and simulation results reveal that the compensated hysteresis comparator exhibits an exceedingly low temperature coefficient. Specifically, with an average hysteresis voltage of 81.67mV, and a temperature range spanning from -40°C to 170°C, the hysteresis voltage undergoes a variation of 15mV, resulting in a temperature coefficient of 0.0714mV/°C.