Electrical Modeling and Performance Analysis of Cu and CNT Based TSV-Bump-RDL

Abstract

The adoption of a feasible bump shape exerts a significant impact on the functionality of a 3D IC. The cylindrical bump structure, considered among the most prevalent shape, endures significant delay, power loss and crosstalk challenges. The tapered based TSV-bump structure recently acquired prominence due to their ultra-low fraction of volume and coupling, resulting in significant alleviation of delay and crosstalk issues. The electrical RLGC modeling has been accomplished for cylindrical, barrel, hourglass and the tapered bump structures along with the impact of coupling, passivation and fringing on the redistribution layer (RDL). In order to validate the proposed TSV bump structure, the quantitative values of a via is compared against the EM and experimental results, and a subsequent investigation have been accomplished for the propagation delay, power dissipation, peak noise, insertion and reflection losses. The proposed via bump structure is remarkable consistence with the experimental results with an average deviation of only 3.51%. In addition, the Finite difference time-domain (FDTD) electromagnetic computation is employed to further examine the performance characteristics. Furthermore, it is worth emphasizing that the tapered bump structure can effectively reduce the propagation delay, power dissipation, peak noise, insertion and reflection losses with an average deviation of 34.83%, 28.62%, 29.98%, 13.57%, and 41.06%, respectively, when compared to the barrel, cylindrical and hourglass bumps.