Solving the Annealing of Mo Interconnects for Next-Gen Integrated Circuits

Abstract

Recent surge in demand for computational power combined with strict constraints on energy consumption requires persistent increase in the density of transistors and memory cells in integrated circuits. Metal interconnects in their current form struggle to follow the size downscaling due to materials limitations at the nanoscale, causing severe performance losses. Next-generation interconnects need new materials, and molybdenum (Mo) is considered the best choice, offering low resistivity, good scalability, and barrierless integration at a low cost. However, it requires annealing at temperatures far exceeding the currently accepted limit. In this work, the challenges of high-temperature annealing of patterned Mo nanowires are looked into, and a new approach is presented to overcome them. It is demonstrated that while a conventional annealing process improves the average grain size, it can also reduce the cross-section area, thus increasing the resistivity. Using high-resolution transmission electron microscopy (TEM) with in situ heating, the evolution of structural features in real time is directly observed. Using insights from these experiments, a cyclic pulsed annealing method is developed, and it is shown that the desired grain structure is achieved in only a few seconds, without forming the surface grooves. These findings can radically facilitate Mo integration, boosting the efficiency of future integrated circuits.