FASQuiC: Flexible Architecture for Scalable Spin Qubit Control

Mathieu Toubeix;Eric Guthmuller;Adrian Evans;Antoine Faurie;Tristan Meunier
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Abstract

As scaling becomes a key issue for large-scale quantum computing, hardware control systems will become increasingly costly in resources. This article presents a compact direct digital synthesis architecture for signal generation adapted for spin qubits that is scalable in terms of waveform accuracy and the number of synchronized channels. The architecture can produce programmable combinations of ramps, frequency combs, and arbitrary waveform generation (AWG) at 5 GS/s, with a worst-case digital feedback latency of 76.8 ns. The field-programmable gate array (FPGA)-based system is highly configurable and takes advantage of bitstream switching to achieve the high flexibility required for scalable calibration. The architecture also provides GHz rate, multiplexed, in-phase and quadrature component, single-side band modulation for scalable reflectometry. This architecture has been validated in hardware on a Xilinx ZCU111 FPGA demonstrating the mixing of complex signals and the quality of the frequency comb generation for multiplexed control and measurement. The key benefits of this design are the increase of controllability of ramps at the digital-to-analog converter (DAC) frequency and the reduction in memory requirements by several orders of magnitude compared with existing AWG-based architectures. The hardware for a single channel is very compact, 2% of ZCU111 logic resources for one DAC lane in the default configuration, leaving significant circuit resources for integrated feedback, calibration, and quantum error correction.
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FASQuiC:可扩展自旋库比特控制的灵活架构
随着扩展成为大规模量子计算的关键问题,硬件控制系统的资源成本将越来越高。本文介绍了一种用于自旋量子比特信号生成的紧凑型直接数字合成架构,该架构在波形精度和同步通道数量方面具有可扩展性。该架构能以 5 GS/s 的速度产生斜坡、频率梳和任意波形生成 (AWG) 的可编程组合,最坏情况下的数字反馈延迟为 76.8 ns。基于现场可编程门阵列(FPGA)的系统具有很高的可配置性,并利用比特流切换实现了可扩展校准所需的高度灵活性。该架构还提供 GHz 速率、多路复用、同相和正交分量、单边带调制,用于可扩展的反射测量。该架构已在 Xilinx ZCU111 FPGA 上进行了硬件验证,演示了复杂信号的混合以及用于多路复用控制和测量的频率梳生成质量。该设计的主要优点是提高了数模转换器 (DAC) 频率斜坡的可控性,与基于 AWG 的现有架构相比,内存需求减少了几个数量级。单通道的硬件非常紧凑,在默认配置下,一个 DAC 通道只需 2% 的 ZCU111 逻辑资源,剩下的大量电路资源可用于集成反馈、校准和量子纠错。
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