{"title":"Charge-sensitive amplifier design for high-speed interface readout front-end ASICs","authors":"Anastasios Michailidis , Vasiliki Gogolou , Thomas Noulis , Jochen Dingfelder","doi":"10.1016/j.aeue.2024.155406","DOIUrl":null,"url":null,"abstract":"<div><p>The design of Charge-Sensitive Amplifiers (CSAs) and the peaking time impact on high-speed interface readout front-end ASICs for 3D pixel detectors with high timing precision, is addressed in this work. The performance of the CSAs is extracted for several architectures, implemented in 180 nm CMOS, 130 nm SiGe BiCMOS, 65 nm CMOS and 22 nm FD-SOI CMOS process nodes for comparison purposes versus technology scaling. The peaking time, the charge gain, the noise and the bandwidth are simulated for all implemented CSAs, while the best CSA candidate performance-wise for high-speed and high timing precision readout ASICs is designated. Furthermore, a full readout chain, capable of resolving particles with a time precision of <span><math><mrow><mo><</mo><mn>200</mn></mrow></math></span> ps, is implemented and simulated. The designed readout ASIC exhibits a Time-Walk performance of <span><math><mrow><mo>≤</mo><mn>180</mn></mrow></math></span> ps, for input charges of <span><math><mrow><mn>6</mn><mo>.</mo><mn>3</mn><mo>−</mo><mn>10</mn><mspace></mspace><mi>k</mi><msup><mrow><mi>e</mi></mrow><mrow><mo>−</mo></mrow></msup></mrow></math></span>, while inducing an equivalent noise charge of <span><math><mrow><mo>≈</mo><mn>570</mn><mspace></mspace><msup><mrow><mi>e</mi></mrow><mrow><mo>−</mo></mrow></msup></mrow></math></span>.</p></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":null,"pages":null},"PeriodicalIF":3.0000,"publicationDate":"2024-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Aeu-International Journal of Electronics and Communications","FirstCategoryId":"94","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S1434841124002917","RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
The design of Charge-Sensitive Amplifiers (CSAs) and the peaking time impact on high-speed interface readout front-end ASICs for 3D pixel detectors with high timing precision, is addressed in this work. The performance of the CSAs is extracted for several architectures, implemented in 180 nm CMOS, 130 nm SiGe BiCMOS, 65 nm CMOS and 22 nm FD-SOI CMOS process nodes for comparison purposes versus technology scaling. The peaking time, the charge gain, the noise and the bandwidth are simulated for all implemented CSAs, while the best CSA candidate performance-wise for high-speed and high timing precision readout ASICs is designated. Furthermore, a full readout chain, capable of resolving particles with a time precision of ps, is implemented and simulated. The designed readout ASIC exhibits a Time-Walk performance of ps, for input charges of , while inducing an equivalent noise charge of .
期刊介绍:
AEÜ is an international scientific journal which publishes both original works and invited tutorials. The journal''s scope covers all aspects of theory and design of circuits, systems and devices for electronics, signal processing, and communication, including:
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AEÜ publishes full papers and letters with very short turn around time but a high standard review process. Review cycles are typically finished within twelve weeks by application of modern electronic communication facilities.