Pub Date : 2026-01-27DOI: 10.1016/j.aeue.2026.156237
Pooja Panda, Ashutosh Mahajan
In this article, we present a dual-band reflective frequency selective surface (FSS) capable of electronically switching between the WLAN bands at 2.45 GHz and 5 GHz. The design employs a loop-based geometry to achieve band-stop functionality, with patterned structures implemented on both the top and bottom layers. Each unit cell integrates four PIN diodes, enabling two distinct switching states. The structure exhibits polarization sensitivity and demonstrates desirable performance under TE polarization. The unit cell dimensions are approximately 0.26 at the lower operating frequency. A parallel biasing scheme is employed, and RF isolation within the DC biasing lines is ensured using six wire-wound inductors per unit cell. A prototype of size 28.8 cm 28.8 cm is fabricated and experimentally characterized under normal incidence. The measured results validate the effectiveness of the proposed FSS, showing strong agreement with simulations. Both simulated and experimental responses show transmission coefficients below -16 dB at the stop bands and insertion losses below 3.3 dB at the pass bands.
在本文中，我们提出了一种双频反射频率选择表面（FSS），能够在2.45 GHz和5 GHz的WLAN频段之间进行电子切换。该设计采用基于环路的几何结构来实现带阻功能，在顶层和底层都实现了图案结构。每个单元集成了四个PIN二极管，实现两种不同的开关状态。该结构具有极化敏感性，在TE极化下表现出良好的性能。在较低的工作频率下，单胞尺寸约为0.26λ0。采用并联偏置方案，并确保直流偏置线内的射频隔离使用六个线绕电感器每个单元单元。制作了尺寸为28.8 cm × 28.8 cm的原型机，并在正入射下进行了实验表征。实测结果验证了所提FSS的有效性，与仿真结果吻合较好。模拟和实验结果均表明，阻带处的传输系数低于-16 dB，通带处的插入损耗低于3.3 dB。
{"title":"Reconfigurable frequency selective surface for dual-band wireless communication and internet of things applications","authors":"Pooja Panda, Ashutosh Mahajan","doi":"10.1016/j.aeue.2026.156237","DOIUrl":"10.1016/j.aeue.2026.156237","url":null,"abstract":"<div><div>In this article, we present a dual-band reflective frequency selective surface (FSS) capable of electronically switching between the WLAN bands at 2.45 GHz and 5 GHz. The design employs a loop-based geometry to achieve band-stop functionality, with patterned structures implemented on both the top and bottom layers. Each unit cell integrates four PIN diodes, enabling two distinct switching states. The structure exhibits polarization sensitivity and demonstrates desirable performance under TE polarization. The unit cell dimensions are approximately 0.26<span><math><msub><mrow><mi>λ</mi></mrow><mrow><mn>0</mn></mrow></msub></math></span> at the lower operating frequency. A parallel biasing scheme is employed, and RF isolation within the DC biasing lines is ensured using six wire-wound inductors per unit cell. A prototype of size 28.8 cm <span><math><mo>×</mo></math></span> 28.8 cm is fabricated and experimentally characterized under normal incidence. The measured results validate the effectiveness of the proposed FSS, showing strong agreement with simulations. Both simulated and experimental responses show transmission coefficients below -16 dB at the stop bands and insertion losses below 3.3 dB at the pass bands.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"207 ","pages":"Article 156237"},"PeriodicalIF":3.2,"publicationDate":"2026-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146080144","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-01-27DOI: 10.1016/j.aeue.2026.156235
Bingjie Zhang , Qiao Chen , Yifan Yin , Hongxin Zhao , Qipeng Wang , Peng Liu , Xiaoxing Yin , Shunli Li
This work proposes a soft-constrained reinforcement learning (SC-RL) framework integrating feasibility prescreening and trust region mechanisms to address physical constraints in high-dimensional parameter space. By embedding penalty rules into the reward function, the framework transforms physical constraints into learnable optimization signals while leveraging proximal policy optimization (PPO) to stabilize policy updates. By establishing a unified abstraction where constraints are defined as mathematical penalty signals, the framework exhibits generalizability across varying antenna structures and radiation mechanisms. Experimental validation on a broadband antipodal linearly tapered slot antenna (ALTSA) and a wideband filtering patch antenna (FPA) demonstrates superior optimization performance and a favorable convergence rate compared to baseline methods. The ALTSA optimized by the proposed framework achieves a 21.1% impedance bandwidth, 6.90% axial ratio bandwidth, and 9.17 dBic peak gain, exceeding the original targets of 16%, 5%, and 8.8 dBic, respectively. While the optimized FPA attains a 23.1% impedance bandwidth and 9.96 dBi peak gain, surpassing its goals of 17% and 9.7 dBi. Furthermore, the convergence speed of this framework is 21.7% and 31.1% faster than standard PPO in the two cases, while outperforming traditional algorithms which are prone to either premature convergence or slower stabilization.
{"title":"Soft-constrained reinforcement learning for antenna optimization with feasibility prescreening","authors":"Bingjie Zhang , Qiao Chen , Yifan Yin , Hongxin Zhao , Qipeng Wang , Peng Liu , Xiaoxing Yin , Shunli Li","doi":"10.1016/j.aeue.2026.156235","DOIUrl":"10.1016/j.aeue.2026.156235","url":null,"abstract":"<div><div>This work proposes a soft-constrained reinforcement learning (SC-RL) framework integrating feasibility prescreening and trust region mechanisms to address physical constraints in high-dimensional parameter space. By embedding penalty rules into the reward function, the framework transforms physical constraints into learnable optimization signals while leveraging proximal policy optimization (PPO) to stabilize policy updates. By establishing a unified abstraction where constraints are defined as mathematical penalty signals, the framework exhibits generalizability across varying antenna structures and radiation mechanisms. Experimental validation on a broadband antipodal linearly tapered slot antenna (ALTSA) and a wideband filtering patch antenna (FPA) demonstrates superior optimization performance and a favorable convergence rate compared to baseline methods. The ALTSA optimized by the proposed framework achieves a 21.1% impedance bandwidth, 6.90% axial ratio bandwidth, and 9.17 dBic peak gain, exceeding the original targets of 16%, 5%, and 8.8 dBic, respectively. While the optimized FPA attains a 23.1% impedance bandwidth and 9.96 dBi peak gain, surpassing its goals of 17% and 9.7 dBi. Furthermore, the convergence speed of this framework is 21.7% and 31.1% faster than standard PPO in the two cases, while outperforming traditional algorithms which are prone to either premature convergence or slower stabilization.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"207 ","pages":"Article 156235"},"PeriodicalIF":3.2,"publicationDate":"2026-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146080141","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-01-27DOI: 10.1016/j.aeue.2026.156236
Uğur Yeşilyurt, Elif Yaman
The vortex electromagnetic wave carrying orbital angular momentum (OAM) increases the spectral efficiency of communication systems. This is achieved by multiplexing the OAM waves in different modes in the same frequency channel due to their orthogonality. A concentric uniform circular array (CUCA) is generally used as a classical method for multiplexing OAM beams. However, CUCA employs a large number of phase-shifting units, which results in a complex feed network. In this paper, a concentric spiral array (CSA) is proposed, which eliminates the need for a complex feed network. CSA utilizes step height to obtain different OAM modes. To make the CSA configuration more compact to achieve high-mode OAM, a concentric spiral sub-array (CSSA) is used, which results in more uniform multiple OAM modes. Additionally, mode purity analyses of the CSA, CSSA, and rearranged CSSA configurations are carried out, and their mode purity performances are evaluated comparatively. Simulation results demonstrate that the proposed method both eliminates the need for external phase shifters and is effective in achieving high-purity OAM multiplexing at the equal divergence angle.
{"title":"Generation of OAM beams with multiple modes with concentric spiral sub-array","authors":"Uğur Yeşilyurt, Elif Yaman","doi":"10.1016/j.aeue.2026.156236","DOIUrl":"10.1016/j.aeue.2026.156236","url":null,"abstract":"<div><div>The vortex electromagnetic wave carrying orbital angular momentum (OAM) increases the spectral efficiency of communication systems. This is achieved by multiplexing the OAM waves in different modes in the same frequency channel due to their orthogonality. A concentric uniform circular array (CUCA) is generally used as a classical method for multiplexing OAM beams. However, CUCA employs a large number of phase-shifting units, which results in a complex feed network. In this paper, a concentric spiral array (CSA) is proposed, which eliminates the need for a complex feed network. CSA utilizes step height to obtain different OAM modes. To make the CSA configuration more compact to achieve high-mode OAM, a concentric spiral sub-array (CSSA) is used, which results in more uniform multiple OAM modes. Additionally, mode purity analyses of the CSA, CSSA, and rearranged CSSA configurations are carried out, and their mode purity performances are evaluated comparatively. Simulation results demonstrate that the proposed method both eliminates the need for external phase shifters and is effective in achieving high-purity OAM multiplexing at the equal divergence angle.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"207 ","pages":"Article 156236"},"PeriodicalIF":3.2,"publicationDate":"2026-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146080143","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We address energy-efficient connected target coverage in wireless sensor networks (WSNs), seeking the smallest active subset of sensors that covers all targets and remains connected to the sink. We propose a Redundancy-Aware Island Genetic Algorithm (RA-IGA). It combines a redundancy-aware mutation with a lightweight deterministic coverage-repair step that aims to activate as few additional sensors as needed to restore feasibility. It also uses a heterogeneous three-island model with periodic elite migration to maintain diversity and improve final quality under the same budget. RA-IGA is benchmarked against the improved genetic algorithm (IGA) and the modified marine predators algorithm (MMPA) across grid and random deployments while varying network size, target count, and field dimensions (up to , , ). RA-IGA consistently selects the fewest active sensors, reducing the active set by 5%–24% vs. IGA and 48%–56% vs. MMPA, with tighter dispersion over 20 seeds. A Friedman test with Nemenyi post-hoc confirms . Because fewer actives generally reduce per-round energy under matched packet and model assumptions, these results suggest longer network lifetime. Ablations indicate that redundancy-aware mutation and repair drive sparsity while preserving feasibility. They also show that the heterogeneous island model helps escape single-population local optima, yielding better final solutions.
{"title":"Redundancy-aware island genetic algorithm for connected target coverage in wireless sensor networks","authors":"Khalil Benhaya , Hocine Riadh , Sonia Sabrina Bendib","doi":"10.1016/j.aeue.2026.156221","DOIUrl":"10.1016/j.aeue.2026.156221","url":null,"abstract":"<div><div>We address energy-efficient connected target coverage in wireless sensor networks (WSNs), seeking the smallest active subset of sensors that covers all targets and remains connected to the sink. We propose a Redundancy-Aware Island Genetic Algorithm (RA-IGA). It combines a redundancy-aware mutation with a lightweight deterministic coverage-repair step that aims to activate as few additional sensors as needed to restore feasibility. It also uses a heterogeneous three-island model with periodic elite migration to maintain diversity and improve final quality under the same budget. RA-IGA is benchmarked against the improved genetic algorithm (IGA) and the modified marine predators algorithm (MMPA) across grid and random deployments while varying network size, target count, and field dimensions (up to <span><math><mrow><mi>N</mi><mo>=</mo><mn>400</mn></mrow></math></span>, <span><math><mrow><mi>K</mi><mo>=</mo><mn>200</mn></mrow></math></span>, <span><math><mrow><mi>L</mi><mo>=</mo><mn>500</mn><mspace></mspace><mi>m</mi></mrow></math></span>). RA-IGA consistently selects the fewest active sensors, reducing the active set by 5%–24% vs. IGA and <span><math><mo>≈</mo></math></span>48%–56% vs. MMPA, with tighter dispersion over 20 seeds. A Friedman test with Nemenyi post-hoc confirms <span><math><mrow><mi>p</mi><mo><</mo><mn>0</mn><mo>.</mo><mn>001</mn></mrow></math></span>. Because fewer actives generally reduce per-round energy under matched packet and model assumptions, these results suggest longer network lifetime. Ablations indicate that redundancy-aware mutation and repair drive sparsity while preserving feasibility. They also show that the heterogeneous island model helps escape single-population local optima, yielding better final solutions.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"207 ","pages":"Article 156221"},"PeriodicalIF":3.2,"publicationDate":"2026-01-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146080142","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-01-24DOI: 10.1016/j.aeue.2026.156223
Fayrouz Shaheen, Eman Azab, Amr Hassan
This paper provides a comprehensive review of analog memristor emulators (Memulators), starting with the theoretical foundation of memristors, historical development, and their physical structures. It then investigates their design methodologies and operational principles in various circuit topologies, encompassing both MOS-based and Active Building Block (ABB)-based designs, which are critically examined, highlighting their unique characteristics, performance trade-offs (including power consumption, layout area, and maximum operating frequency), and inherent design considerations. Addressing the lack of standardisation in the field, a concrete, minimal benchmark suite is proposed, specifying test signals and robustness tests to ensure reproducible characterisation. A detailed comparative analysis of recent analog memulator circuits is presented, employing a defined Figure of Merit (FoM) and introducing a novel framework of qualitative comparison tables. Unlike traditional performance listings, this framework meticulously evaluates designs based on validation rigour (distinguishing simulation from experimental silicon), architectural versatility, and electronic tunability, providing a systematic metric for practical deployment readiness. Furthermore, a critical analysis of implementation challenges — including sneak paths, device variability, and forming-free operation — synthesises how different topologies mitigate these issues. Key case studies of fabricated memulator designs are also highlighted, illustrating practical realisation and system-level application. The paper further explores a wide range of applications, with particular emphasis on neuromorphic computing and chaotic oscillators for secure communications, demonstrating their practical significance in modern electronics. Finally, recent advancements and innovations from the literature are summarised, alongside a thorough discussion of prevailing research trends and promising future research directions aimed at overcoming existing limitations and unlocking new capabilities.
{"title":"A survey on analog memristor emulators and their applications","authors":"Fayrouz Shaheen, Eman Azab, Amr Hassan","doi":"10.1016/j.aeue.2026.156223","DOIUrl":"10.1016/j.aeue.2026.156223","url":null,"abstract":"<div><div>This paper provides a comprehensive review of analog memristor emulators (Memulators), starting with the theoretical foundation of memristors, historical development, and their physical structures. It then investigates their design methodologies and operational principles in various circuit topologies, encompassing both MOS-based and Active Building Block (ABB)-based designs, which are critically examined, highlighting their unique characteristics, performance trade-offs (including power consumption, layout area, and maximum operating frequency), and inherent design considerations. Addressing the lack of standardisation in the field, a concrete, minimal benchmark suite is proposed, specifying test signals and robustness tests to ensure reproducible characterisation. A detailed comparative analysis of recent analog memulator circuits is presented, employing a defined Figure of Merit (FoM) and introducing a novel framework of qualitative comparison tables. Unlike traditional performance listings, this framework meticulously evaluates designs based on validation rigour (distinguishing simulation from experimental silicon), architectural versatility, and electronic tunability, providing a systematic metric for practical deployment readiness. Furthermore, a critical analysis of implementation challenges — including sneak paths, device variability, and forming-free operation — synthesises how different topologies mitigate these issues. Key case studies of fabricated memulator designs are also highlighted, illustrating practical realisation and system-level application. The paper further explores a wide range of applications, with particular emphasis on neuromorphic computing and chaotic oscillators for secure communications, demonstrating their practical significance in modern electronics. Finally, recent advancements and innovations from the literature are summarised, alongside a thorough discussion of prevailing research trends and promising future research directions aimed at overcoming existing limitations and unlocking new capabilities.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"207 ","pages":"Article 156223"},"PeriodicalIF":3.2,"publicationDate":"2026-01-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146080145","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-01-22DOI: 10.1016/j.aeue.2026.156222
Debanjan Dhara, Ranajay Paul , Suvarun Dalapati
For a single-phase full-bridge inverter, hybrid PWM switching is more preferable for continuous operation due to its reduced switching losses and lower thermal stress on individual semiconductor switches, without compromising in PWM output. On the other hand, One-Cycle-Control (OCC) is a non-linear control technique which is used in power-electronic converters for achieving very fast response and for compensating the dead-time distortion. This paper presents a novel closed-loop Hybrid PWM based OCC (HPOCC) technique for single-phase full-bridge inverter, generating switching pulses in hybrid PWM mode, thereby reducing switching losses, and also has the control dynamics similar to conventional-OCC. The proposed technique not only uses a single resettable integrator instead of two, as seen in conventional-OCC based single-phase full-bridge inverter, but also delivers improved quality output voltage, as compared to conventional OCC based single-phase full-bridge inverters. All these advantages make this technique a superior alternative to conventional-OCC. Thus, this PWM technique can fulfill the requirement for low switching-loss, fast dynamic performance and low total-harmonic-distortion (THD) in inverter-output. The performance of this technique is validated through mathematical analysis, simulation on a digital platform and experiments on a laboratory set-up, which confirm its superior nature as compared to conventional-OCC and Sine-PWM techniques.
{"title":"An improved closed-loop PWM control technique for single-phase full-bridge voltage source inverter","authors":"Debanjan Dhara, Ranajay Paul , Suvarun Dalapati","doi":"10.1016/j.aeue.2026.156222","DOIUrl":"10.1016/j.aeue.2026.156222","url":null,"abstract":"<div><div>For a single-phase full-bridge inverter, hybrid PWM switching is more preferable for continuous operation due to its reduced switching losses and lower thermal stress on individual semiconductor switches, without compromising in PWM output. On the other hand, One-Cycle-Control (OCC) is a non-linear control technique which is used in power-electronic converters for achieving very fast response and for compensating the dead-time distortion. This paper presents a novel closed-loop Hybrid PWM based OCC (HPOCC) technique for single-phase full-bridge inverter, generating switching pulses in hybrid PWM mode, thereby reducing switching losses, and also has the control dynamics similar to conventional-OCC. The proposed technique not only uses a single resettable integrator instead of two, as seen in conventional-OCC based single-phase full-bridge inverter, but also delivers improved quality output voltage, as compared to conventional OCC based single-phase full-bridge inverters. All these advantages make this technique a superior alternative to conventional-OCC. Thus, this PWM technique can fulfill the requirement for low switching-loss, fast dynamic performance and low total-harmonic-distortion (THD) in inverter-output. The performance of this technique is validated through mathematical analysis, simulation on a digital platform and experiments on a laboratory set-up, which confirm its superior nature as compared to conventional-OCC and Sine-PWM techniques.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"207 ","pages":"Article 156222"},"PeriodicalIF":3.2,"publicationDate":"2026-01-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146080291","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper proposes a design method of a wideband Doherty power amplifier (DPA) using resistive continuous class-J mode with harmonic load modulation suppression, aiming to achieve high efficiency at back-off output powers (BOPs) across a wide frequency band. Firstly, based on theoretical impedance analysis of the resistive continuous class-J mode, the optimum load impedances under both saturation and BOP conditions are identified for DPA design. Then, combined with the load modulation theory, optimization objective functions are formulated for the peaking output matching networks (OMNs) design and optimization. In addition, to control the carrier second harmonic impedance during the load modulation, the peaking OMN using fragment-type matching circuit is used to suppress harmonic load modulation. For verification, a DPA operating at 2.0–3.4 GHz is designed and measured. The results show that the DPA achieves saturated output power of 43.1–44.4 dBm across the entire frequency band, with drain efficiencies of 59.1%–72% at saturation and 50%–58.9% at 6 dB BOP.
{"title":"Design of wideband resistive continuous class-J Doherty power amplifier with harmonic load modulation suppression","authors":"Wa Kong, Wenya Liu, Hongyan Fu, Hui Ma, Wence Zhang, Jing Xia","doi":"10.1016/j.aeue.2026.156226","DOIUrl":"10.1016/j.aeue.2026.156226","url":null,"abstract":"<div><div>This paper proposes a design method of a wideband Doherty power amplifier (DPA) using resistive continuous class-J mode with harmonic load modulation suppression, aiming to achieve high efficiency at back-off output powers (BOPs) across a wide frequency band. Firstly, based on theoretical impedance analysis of the resistive continuous class-J mode, the optimum load impedances under both saturation and BOP conditions are identified for DPA design. Then, combined with the load modulation theory, optimization objective functions are formulated for the peaking output matching networks (OMNs) design and optimization. In addition, to control the carrier second harmonic impedance during the load modulation, the peaking OMN using fragment-type matching circuit is used to suppress harmonic load modulation. For verification, a DPA operating at 2.0–3.4 GHz is designed and measured. The results show that the DPA achieves saturated output power of 43.1–44.4 dBm across the entire frequency band, with drain efficiencies of 59.1%–72% at saturation and 50%–58.9% at 6 dB BOP.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"207 ","pages":"Article 156226"},"PeriodicalIF":3.2,"publicationDate":"2026-01-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146025078","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper introduces a novel Phase Frequency Detector (PFD) based on Dynamic MOS Current Mode Logic (DyCML), designed for low-power, high-speed frequency synthesizers. The proposed PFD eliminates the need for a reset path, thereby removing dead and blind zones and improving output linearity across a full phase range from –π to π. The DyCML approach offers inherent advantages such as low static power dissipation, high-speed switching, and enhanced noise immunity through differential, current-mode operation. Design parameters were optimized using Taguchi Design of Experiments (DoE) and Analysis of Variance (ANOVA) techniques to achieve optimal performance. The optimized PFD achieves a phase noise of –159.41 dBc/Hz, power consumption of 5.822 μW, maximum operating frequency of 6.91 GHz, and a delay of 42.76 ps. The layout area is 793.27 μm2, and the design attains a figure-of-merit of –168.55 dBc/Hz. Robustness is validated through Process-Voltage-Temperature and Monte Carlo analysis, showing close agreement between post-layout and pre-layout results. Integrated into a PLL frequency synthesizer, the PFD achieves a lock time of 500 ns at output frequency 3.8 GHz, with low jitter and minimal reference spur. The design is implemented in Cadence Virtuoso using a 0.18 μm SCL CMOS process at a 1.8 V supply.
{"title":"Design and optimization of a low-power dynamic MCML-based phase-frequency detector using Taguchi DoE and ANOVA for frequency synthesizers with fast-locking of 0.5 μs","authors":"Dheeraj Singh Rajput , Bharat Choudhary , Archana Singhal , Dharmendar Boolchandani","doi":"10.1016/j.aeue.2026.156214","DOIUrl":"10.1016/j.aeue.2026.156214","url":null,"abstract":"<div><div>This paper introduces a novel Phase Frequency Detector (PFD) based on Dynamic MOS Current Mode Logic (DyCML), designed for low-power, high-speed frequency synthesizers. The proposed PFD eliminates the need for a reset path, thereby removing dead and blind zones and improving output linearity across a full phase range from –π to π. The DyCML approach offers inherent advantages such as low static power dissipation, high-speed switching, and enhanced noise immunity through differential, current-mode operation. Design parameters were optimized using Taguchi Design of Experiments (DoE) and Analysis of Variance (ANOVA) techniques to achieve optimal performance. The optimized PFD achieves a phase noise of –159.41 dBc/Hz, power consumption of 5.822 μW, maximum operating frequency of 6.91 GHz, and a delay of 42.76 ps. The layout area is 793.27 μm<sup>2</sup>, and the design attains a figure-of-merit of –168.55 dBc/Hz. Robustness is validated through Process-Voltage-Temperature and Monte Carlo analysis, showing close agreement between post-layout and pre-layout results. Integrated into a PLL frequency synthesizer, the PFD achieves a lock time of 500 ns at output frequency 3.8 GHz, with low jitter and minimal reference spur. The design is implemented in Cadence Virtuoso using a 0.18 μm SCL CMOS process at a 1.8 V supply.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"207 ","pages":"Article 156214"},"PeriodicalIF":3.2,"publicationDate":"2026-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146025076","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-01-16DOI: 10.1016/j.aeue.2026.156212
Jianhong Xiang, Nan Zhang, Linyu Wang
In massive multiple-input multiple-output (MIMO) systems, accurate downlink channel state information (CSI) is essential for signal preprocessing, yet achieving high-fidelity feedback under limited overhead remains challenging. To address this issue, and motivated by the sparsity and strong local spatial structure of CSI, we propose an all-domain joint CSI feedback network based on multi-scale pooling, termed APCNet. The encoder of this network introduces a spatial–frequency domain branch on the basis of the classical angle–delay domain (ADD) convolution branch, aiming to provide complete physical feature priors for the reconstruction process, fundamentally solving the information loss issue caused by single-domain modeling. On the decoder side, we propose a PCformer architecture, constructing a physically aligned extraction–reconstruction pipeline: utilizing the multi-scale pooling module for statistical extraction of multipath features, and combining the ConvNeXt Block for fine-grained restoration of spatial details. This compensates for the shortcomings of the universal self-attention mechanism in local structure representation. Experimental results demonstrate that APCNet achieves an average improvement of 7.96% in reconstruction accuracy across various compression rates for outdoor scenes, while delivering leading or competitive performance for most compression rates in indoor scenes.
{"title":"APCNet: A multi-scale pooling enhanced all-domain joint CSI feedback network for massive MIMO systems","authors":"Jianhong Xiang, Nan Zhang, Linyu Wang","doi":"10.1016/j.aeue.2026.156212","DOIUrl":"10.1016/j.aeue.2026.156212","url":null,"abstract":"<div><div>In massive multiple-input multiple-output (MIMO) systems, accurate downlink channel state information (CSI) is essential for signal preprocessing, yet achieving high-fidelity feedback under limited overhead remains challenging. To address this issue, and motivated by the sparsity and strong local spatial structure of CSI, we propose an all-domain joint CSI feedback network based on multi-scale pooling, termed APCNet. The encoder of this network introduces a spatial–frequency domain branch on the basis of the classical angle–delay domain (ADD) convolution branch, aiming to provide complete physical feature priors for the reconstruction process, fundamentally solving the information loss issue caused by single-domain modeling. On the decoder side, we propose a PCformer architecture, constructing a physically aligned extraction–reconstruction pipeline: utilizing the multi-scale pooling module for statistical extraction of multipath features, and combining the ConvNeXt Block for fine-grained restoration of spatial details. This compensates for the shortcomings of the universal self-attention mechanism in local structure representation. Experimental results demonstrate that APCNet achieves an average improvement of 7.96% in reconstruction accuracy across various compression rates for outdoor scenes, while delivering leading or competitive performance for most compression rates in indoor scenes.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"207 ","pages":"Article 156212"},"PeriodicalIF":3.2,"publicationDate":"2026-01-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146025079","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-01-16DOI: 10.1016/j.aeue.2026.156216
P. Manikandan
This work proposes a fast transient, dynamically biased cascoded flipped voltage follower low-dropout (LDO) regulator. The proposed LDO is constructed based on a single-stage error amplifier (EA) and a cascoded flipped voltage follower. The proposed error amplifier dynamically biases the CAFVF and enhances the transient and stability performance of the LDO regulator. This work uses three different feed-forward transconductors along with one miller and two feed-forward small compensatory capacitors. Two of these feed-forward transconductors and three small compensation capacitors generate two low-frequency left-half-plane (LHP) zeros in conjunction with the self-feed-forward path. These LHP zeros are unaffected by load conditions and provide consistent phase lead for all the load cases. Another feed-forward transconductor converts the load-dependent right-half-plane (RHP) Miller zero to an LHP zero. The load-dependent LHP zero appears closer to the unity gain frequency (UGF) for a lightly loaded LDO, improving its stability under light load situations. The proposed frequency compensation technique stabilizes the LDO for load currents ranging from 0 to , with a maximum load capacitor of . The proposed LDO is designed using UMC CMOS technology and implemented with the Cadence Virtuoso tool. With a maximum quiescent current of , the proposed LDO achieves a minimum good slew rate (SR) of and minimum unity gain frequency of , allowing it to settle faster with a settling time of . The reliability and robustness of the proposed LDO are verified using the process corners with an extreme temperature range and 200-point Monte Carlo simulations.
{"title":"A fast transient dynamically biased output capacitor-less cascoded flipped voltage follower (CAFVF) LDO regulator","authors":"P. Manikandan","doi":"10.1016/j.aeue.2026.156216","DOIUrl":"10.1016/j.aeue.2026.156216","url":null,"abstract":"<div><div>This work proposes a fast transient, dynamically biased cascoded flipped voltage follower low-dropout (LDO) regulator. The proposed LDO is constructed based on a single-stage error amplifier (EA) and a cascoded flipped voltage follower. The proposed error amplifier dynamically biases the CAFVF and enhances the transient and stability performance of the LDO regulator. This work uses three different feed-forward transconductors along with one miller and two feed-forward small compensatory capacitors. Two of these feed-forward transconductors and three small compensation capacitors generate two low-frequency left-half-plane (LHP) zeros in conjunction with the self-feed-forward path. These LHP zeros are unaffected by load conditions and provide consistent phase lead for all the load cases. Another feed-forward transconductor converts the load-dependent right-half-plane (RHP) Miller zero to an LHP zero. The load-dependent LHP zero appears closer to the unity gain frequency (UGF) for a lightly loaded LDO, improving its stability under light load situations. The proposed frequency compensation technique stabilizes the LDO for load currents ranging from 0 to <span><math><mrow><mn>30</mn><mspace></mspace><mi>mA</mi></mrow></math></span>, with a maximum load capacitor of <span><math><mrow><mn>50</mn><mspace></mspace><mi>pF</mi></mrow></math></span>. The proposed LDO is designed using UMC <span><math><mrow><mn>90</mn><mspace></mspace><mi>nm</mi></mrow></math></span> CMOS technology and implemented with the Cadence Virtuoso tool. With a maximum quiescent current of <span><math><mrow><mn>91</mn><mo>.</mo><mn>3</mn><mspace></mspace><mi>μ</mi><mi>A</mi></mrow></math></span>, the proposed LDO achieves a minimum good slew rate (SR) of <span><math><mrow><mn>30</mn><mspace></mspace><mi>V</mi><mo>/</mo><mi>μ</mi><mi>s</mi></mrow></math></span> and minimum unity gain frequency of <span><math><mrow><mn>15</mn><mo>.</mo><mn>7</mn><mspace></mspace><mi>MHz</mi></mrow></math></span>, allowing it to settle faster with a settling time of <span><math><mrow><mn>30</mn><mspace></mspace><mi>ns</mi></mrow></math></span>. The reliability and robustness of the proposed LDO are verified using the process corners with an extreme temperature range and 200-point Monte Carlo simulations.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"207 ","pages":"Article 156216"},"PeriodicalIF":3.2,"publicationDate":"2026-01-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145982036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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