Aeu-International Journal of Electronics and Communications最新文献

Highly-miniaturized microfluidically-based frequency reconfigurable antenna diplexer employing half-mode SIRW 采用半模 SIRW 的高度微型化微流控频率可重构天线双工器

IF 3 3区计算机科学 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

Aeu-International Journal of Electronics and Communications

Pub Date : 2024-09-28 DOI: 10.1016/j.aeue.2024.155534

This article introduces a super-miniaturized frequency reconfigurable antenna diplexer based on microfluidic techniques. The proposed structure is developed using a half-mode substrate-integrated rectangular waveguide (HMSIRW). The antenna architecture consists of two HMSIRW cavities loaded with L-shaped slots, which are excited by two microstrip feedlines to realize two distinct radiating frequency bands. The footprint of the antenna diplexer is miniaturized by using the half-mode cavities. Further size reduction is achieved by the capacitive loading of the slots. The design evaluation, radiation mechanism, parametric analysis, and equivalent circuit model are discussed in detail. The empty fluidic vias are drilled on the bottom plane of the cavities and poured with various dielectric liquids to obtain independent frequency reconfigurability at two operating bands. For validation, a frequency reconfigurable antenna diplexer is designed, manufactured, and demonstrated experimentally. The measured results show that the return loss, isolation, and realized gains are greater than −20 dB, 28 dB, and 3.3 dBi, respectively, while ensuring small footprint of only 0.071λ_g². The fabricated diplexer exhibits a frequency reconfiguration range greater than 17 % at both frequency bands.

本文介绍了一种基于微流体技术的超微型频率可重构天线双工器。所提出的结构是利用半模基底集成矩形波导（HMSIRW）开发的。天线结构由两个装有 L 形槽的 HMSIRW 腔体组成，这两个腔体由两条微带馈线激励，以实现两个不同的辐射频段。通过使用半模空腔，天线双工器的占地面积实现了小型化。槽的电容加载实现了尺寸的进一步缩小。本文详细讨论了设计评估、辐射机制、参数分析和等效电路模型。在空腔底面钻空流体通孔，并注入各种介质液体，以获得两个工作频带的独立频率可重构性。为进行验证，设计、制造并实验演示了频率可重构天线双工器。测量结果表明，回波损耗、隔离度和实现增益分别大于-20 dB、28 dB和3.3 dBi，同时确保了仅0.071λg2的小尺寸。所制造的双工器在两个频段的频率重新配置范围均大于 17%。

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引用次数: 0

Analysis and design of voltage-source parallel resonant class E/F3 inverter 电压源并联谐振式 E/F3 类逆变器的分析与设计

IF 3 3区计算机科学 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

Aeu-International Journal of Electronics and Communications

Pub Date : 2024-09-27 DOI: 10.1016/j.aeue.2024.155542

In this paper, a detailed mathematical analysis process of the voltage-source parallel resonant (VSPR) class

E / F_{3}

inverter at 50% duty ratio is proposed. Combining the advantages of VSPR class E and F inverters, the performance of the proposed inverter can be improved greatly compared to the traditional. The transistor in the VSPR class

E / F_{3}

inverter is satisfied with zero-voltage switching(ZVS) and zero-voltage derivative switching(ZVDS) conditions. Moreover, two design freedoms can be obtained and the proposed analysis process is based on them, which can provide more flexible selections. Finally, a VSPR class

E / F_{3}

inverter is fabricated and the experiment is carried out. The measured normalized peak transistor voltage decreases by 25.6%. The output power reaches 5.06 W, and the efficiency reaches 93.75%. The measured results are well agreed with the theoretical and simulated.

本文提出了占空比为 50% 的电压源并联谐振 (VSPR) E/F3 类逆变器的详细数学分析过程。结合 VSPR E 类和 F 类逆变器的优点，与传统逆变器相比，本文提出的逆变器性能有了很大提高。VSPR E/F3 类逆变器中的晶体管满足零电压开关（ZVS）和零电压导数开关（ZVDS）条件。此外，还可获得两种设计自由度，并在此基础上提出分析流程，从而提供更灵活的选择。最后，制作了一个 VSPR E/F3 级逆变器并进行了实验。测得的归一化晶体管峰值电压降低了 25.6%。输出功率达到 5.06 W，效率达到 93.75%。测量结果与理论和模拟结果完全吻合。

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引用次数: 0

A simple way to achieve planar excitation of arc-shaped array feeds in two-dimensional beam-steerable spherical lens antenna 在二维波束稳定球透镜天线中实现弧形阵列馈电平面激励的简单方法

IF 3 3区计算机科学 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

Aeu-International Journal of Electronics and Communications

Pub Date : 2024-09-26 DOI: 10.1016/j.aeue.2024.155536

In this article, a simple technique for achieving planar excitation positions of arc-shaped array feeds in a two-dimensional (2D) beam-steerable spherical lens antenna (SLA) is proposed. Specifically, a cuboid solder model is introduced to connect the feedlines of the feeds with the coaxial probe. An equivalent circuit model of the bowtie feed unit with solder is proposed to illustrate the impact of the introduced solder on the port matching. Additionally, the excitation position is altered by extending the microstrip feedline, which does not change the radiation structure of the feed nor affect its phase center. Subsequently, a homogeneous dielectric SLA with a 139-element bowtie-shaped dipole feed array is constructed to verify the planar excitation position scheme for the arc-shaped array feeds, which facilitates system integration. The theoretical calculation formulas for the beam pointing angles of numerous beams are also proposed. In the fabricated prototype, all feeds exhibit an overlapping bandwidth of 31–36.7 GHz for reflection coefficients, with the coupling less than -20 dB. The 139 switched beams cover a 2D continuous beam space of [

-

33°, 33°], with adjacent beam crossover levels around -4 dB. The measured peak gain is 28.7 dBi at 34.5 GHz, with an aperture efficiency of 57%.

本文提出了一种在二维（2D）波束可转向球面透镜天线（SLA）中实现弧形阵列馈线平面激励位置的简单技术。具体来说，本文引入了一个立方体焊接模型来连接馈线与同轴探针。提出了带焊料的弓形馈电单元等效电路模型，以说明引入焊料对端口匹配的影响。此外，通过延长微带馈线来改变激励位置，这不会改变馈线的辐射结构，也不会影响其相位中心。随后，构建了一个带有 139 个元件的弓形偶极子馈电阵列的均质介质 SLA，以验证弧形阵列馈电的平面激励位置方案，从而方便了系统集成。此外，还提出了众多光束指向角的理论计算公式。在制作的原型中，所有馈电的反射系数都显示出 31-36.7 GHz 的重叠带宽，耦合小于 -20 dB。139 个切换波束覆盖[-33°, 33°]的二维连续波束空间，相邻波束交叉电平约为 -4 dB。在 34.5 GHz 时，测得的峰值增益为 28.7 dBi，孔径效率为 57%。

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引用次数: 0

Radar pre-sorting algorithm based on autoencoder and LSTM 基于自动编码器和 LSTM 的雷达预排序算法

IF 3 3区计算机科学 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

Aeu-International Journal of Electronics and Communications

Pub Date : 2024-09-24 DOI: 10.1016/j.aeue.2024.155535

As the electromagnetic environment becomes increasingly complex, most current radar signal sorting methods are unsustainable. They often perform poorly when dealing with unknown radar types and low-frequency radar pulse data. This paper introduces a radar pre-sorting algorithm based on autoencoder and LSTM. The algorithm utilizes multi-dimensional information such as pulse width, carrier frequency, and time of arrival. The autoencoder network is employed to achieve automatic feature extraction and clustering, enhancing the extraction of latent features in the data. The proposed network model mainly consists of three parts: an encoding module composed of a convolutional neural network (CNN), a feature aggregation module composed of long short-term memory (LSTM), and a decoding module obtained through a convolutional autoencoder, referred to as CLDE (CNN-LSTM-Decode). The encoding module extracts features from multi-dimensional data to obtain compressed features, the feature accumulation module processes the compressed features, further extracting hidden features between pulses. Subsequently, the decoding module determines the pulse modulation type of each pulse, achieving the purpose of radar pulse signal pre-sorting. Simulation results show that this network structure effectively pre-classifies unknown radar signals and has a high recognition rate for low-frequency pulses. Additionally, CLDE exhibits high reliability and stability in environments with pulse loss.

随着电磁环境日益复杂，目前大多数雷达信号分类方法都难以为继。在处理未知雷达类型和低频雷达脉冲数据时，它们往往表现不佳。本文介绍了一种基于自动编码器和 LSTM 的雷达预排序算法。该算法利用脉冲宽度、载波频率和到达时间等多维信息。采用自动编码器网络实现自动特征提取和聚类，增强了对数据中潜在特征的提取。所提出的网络模型主要由三部分组成：由卷积神经网络（CNN）组成的编码模块、由长短期记忆（LSTM）组成的特征聚合模块，以及通过卷积自动编码器获得的解码模块，简称为 CLDE（CNN-LSTM-Decode）。编码模块从多维数据中提取特征，得到压缩特征，特征积累模块处理压缩特征，进一步提取脉冲之间的隐藏特征。随后，解码模块确定每个脉冲的调制类型，达到雷达脉冲信号预分选的目的。仿真结果表明，这种网络结构能有效地对未知雷达信号进行预分类，对低频脉冲具有较高的识别率。此外，CLDE 在脉冲丢失的环境中表现出很高的可靠性和稳定性。

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引用次数: 0

Radiation-hardened latch design with triple-node-upset recoverability 抗辐射加固闩锁设计，具有三节点重置恢复能力

IF 3 3区计算机科学 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

Aeu-International Journal of Electronics and Communications

Pub Date : 2024-09-24 DOI: 10.1016/j.aeue.2024.155539

As CMOS technology scales down the susceptibility of integrated circuits to radiation effects makes them vulnerable to single-event upsets (SEUs) that may cause the formation of soft errors. In nanometer technologies, SEUs have the potential to impact many nodes within a circuit, resulting to Multiple Node Upsets (MNUs). Several techniques have been proposed to deal with SEUs that simultaneously influence either one, two, or three nodes. This paper presents a latch design that is capable of tolerating up to triple-node upsets (TNUs). Hardware redundancy is exploited to store data in many nodes inside the latch, along with a multiple feedback scheme that provides the recovery of the correct latch state in the case of SEUs. The proposed method provides faster recovery time after an SEU, and at the same time reduced power-delay and area-power-delay products with respect to existing solutions in the literature.

随着 CMOS 技术规模的缩小，集成电路对辐射效应的敏感性使其容易受到可能导致软错误形成的单次事件中断（SEU）的影响。在纳米技术中，SEU 有可能会影响电路中的许多节点，从而导致多节点故障（MNU）。目前已提出了几种技术来处理同时影响一个、两个或三个节点的 SEU。本文提出的锁存器设计能够承受多达三个节点的故障（TNU）。利用硬件冗余将数据存储在锁存器内的多个节点中，并采用多重反馈方案，在 SEU 发生时恢复正确的锁存器状态。与文献中的现有解决方案相比，所提出的方法能在 SEU 发生后提供更快的恢复时间，同时减少功率-延迟和面积-功率-延迟乘积。

引用次数: 0

Compact dual-band enhanced bandwidth 5G mm – wave MIMO dielectric resonator antenna utilizing metallic strips 利用金属带的紧凑型双频增强带宽 5G 毫米波 MIMO 介质谐振器天线

IF 3 3区计算机科学 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

Aeu-International Journal of Electronics and Communications

Pub Date : 2024-09-24 DOI: 10.1016/j.aeue.2024.155510

A compact dual-band Multiple-Input Multiple-Output Dielectric Resonator Antenna with improved bandwidth for 5G mm-wave applications is presented. Two rectangular DRAs mounted on a substrate backed ground plane are excited by microstrip feed through aperture coupling. Notches cut out from center of the DRAs helps to achieve a dual-band response with improved bandwidth by exciting several modes. The isolation between the DRAs is achieved by appropriately positioning metallic strips on walls on of the DRAs. A dual-band response with enhanced bandwidth and mutual coupling reduction. The impedance bandwidth for the proposed design is between 26.5–30 GHz (12.4 %) and 34.2–40 GHz (15.6 %). The maximum isolation achieved in the lower band is 32 dB and above 45 dB in the upper band. The overall size of the design is 1.88λ_o x 0.94λ_o x 0.20λ_o. The design procedure is described, and the role of decoupling strips are explained. A prototype is fabricated and measured to validate the proposed design.

本文介绍了一种紧凑型双频多输入多输出介质谐振器天线，它具有更高的带宽，适用于 5G 毫米波应用。两个矩形介质谐振器安装在一个基底面上，通过孔隙耦合由微带馈电激励。从 DRA 中心切出的凹槽有助于实现双频响应，并通过激发多种模式提高带宽。DRA 之间的隔离是通过在 DRA 壁上适当放置金属条来实现的。双频响应，带宽增强，相互耦合减小。拟议设计的阻抗带宽介于 26.5-30 千兆赫（12.4%）和 34.2-40 千兆赫（15.6%）之间。低频段实现的最大隔离度为 32 dB，高频段超过 45 dB。设计的总体尺寸为 1.88λo x 0.94λo x 0.20λo。介绍了设计程序，并解释了去耦条的作用。制作并测量了一个原型，以验证所提出的设计。

引用次数: 0

Priority-based band sharing for secondary users in cognitive radio networks 认知无线电网络中二级用户基于优先级的频段共享

IF 3 3区计算机科学 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

Aeu-International Journal of Electronics and Communications

Pub Date : 2024-09-23 DOI: 10.1016/j.aeue.2024.155533

To improve wireless spectrum utilization, cognitive radio networks (CRNs) allow secondary users (SUs) opportunistic access to the frequency bands owned by primary users (PUs), when such PUs are inactive. A fully distributed CRN architecture is quite favorable, as it does not require any centralized scheduling, nor does it require coordination between SUs via a common control channel. This can reduce cost and avoid single point-of-failure issues. However, uncoordinated access to the spectrum by competing SUs, if not done judiciously, can cause excessive collisions and limit performance, which can be detrimental to the usefulness of CRNs, especially if some SUs have urgent traffic to send. Hence, we present a novel protocol to support traffic with multiple classes of priority within a fully distributed CRN. In such protocol, competing SUs attempt to access the spectrum autonomously, but rationally, based on their priority level, opting to transmit their packets when it is beneficial to both the SU itself and also to the overall system performance. Simulations confirm that the proposed protocol achieves excellent overall network performance, while ensuring that higher priority packets experience higher throughput and smaller delay compared to lower priority packets.

为了提高无线频谱的利用率，认知无线电网络（CRN）允许次要用户（SU）在主要用户（PU）不活动时伺机访问主要用户（PU）拥有的频段。完全分布式的 CRN 架构非常有利，因为它不需要任何集中式调度，也不需要通过共同的控制信道在 SU 之间进行协调。这可以降低成本，避免单点故障问题。但是，如果竞争性 SU 对频谱的访问不协调，可能会导致过度碰撞并限制性能，这可能会损害 CRN 的效用，尤其是在一些 SU 有紧急流量要发送的情况下。因此，我们提出了一种新颖的协议，以支持完全分布式 CRN 中具有多个优先级的流量。在这种协议中，相互竞争的 SU 会根据其优先级自主但合理地访问频谱，并在对 SU 本身和整个系统性能有利时选择传输其数据包。仿真证实，建议的协议实现了出色的整体网络性能，同时确保较高优先级的数据包与较低优先级的数据包相比，具有更高的吞吐量和更小的延迟。

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引用次数: 0

Pico-ampere resolution current measurement circuit using Gm-C filter sigma-delta modulator for low-power nanopore DNA sequencing 使用 Gm-C 滤波器 sigma-delta 调制器的皮安培分辨率电流测量电路，用于低功耗纳米孔 DNA 测序

IF 3 3区计算机科学 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

Aeu-International Journal of Electronics and Communications

Pub Date : 2024-09-19 DOI: 10.1016/j.aeue.2024.155508

New generation DNA sequencers use an array of electrochemical cells equipped with nanopores, which produce pico-ampere current levels. Due to the large number of channels, low current levels and bandwidths in the order of a few kHz, in the design of these readout circuits, 2D arrays of in-channel, low noise and low power analog to digital converters are preferred. Previously many different sigma-delta modulators have been presented to convert the nanopore current signal into a digital code. Conventionally, the opamps required in these converters will eventually increase the power dissipation of each channel. In this paper a novel Gm-C filter based second order sigma-delta converter is proposed. In the given design, rather than relying on multiple opamps to achieve the necessary gain and noise performance, only a 4 transistor Gm block is used. Evaluations show that while the input referred noise remains close to previous methods, the power dissipation is considerably reduced. A prototype is also implemented to show the effectiveness of the approach. In a 180-nm design, an ENOB of 12.16 bits, RMS input referred noise of 0.2 pA at 10 kHz bandwidth and power dissipation of 8.27 μW is obtained per channel.

新一代 DNA 测序仪使用配备纳米孔的电化学电池阵列，可产生皮安培级电流。由于通道数量多、电流水平低、带宽仅为几千赫兹，在设计这些读出电路时，二维通道内阵列、低噪声、低功耗模数转换器成为首选。以前曾出现过许多不同的 sigma-delta 调制器，用于将纳米孔电流信号转换成数字代码。传统上，这些转换器所需的运算放大器最终会增加每个通道的功耗。本文提出了一种基于 Gm-C 滤波器的新型二阶 sigma-delta 转换器。在该设计中，只使用了一个 4 晶体管 Gm 块，而不是依靠多个运算放大器来实现必要的增益和噪声性能。评估结果表明，虽然输入参考噪声仍与以前的方法接近，但功耗却大大降低。此外，还实现了一个原型，以显示该方法的有效性。在 180 纳米设计中，每个通道的 ENOB 为 12.16 位，10 kHz 带宽下的 RMS 输入参考噪声为 0.2 pA，功耗为 8.27 μW。

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引用次数: 0

Investigation and analysis of design techniques for ultra-wideband CMOS on-chip dipole antennas for 6G sub-THz applications 针对 6G sub-THz 应用的超宽带 CMOS 片上偶极子天线设计技术的研究与分析

IF 3 3区计算机科学 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

Aeu-International Journal of Electronics and Communications

Pub Date : 2024-09-18 DOI: 10.1016/j.aeue.2024.155532

This article explores different techniques to improve the impedance bandwidth of on-chip dipole antennas in the sub-THz frequency range. Increasing the area of the dipole antenna has shown considerable improvement in bandwidth. However, this violates the design rule checks (DRC) of the foundry. Various topologies, such as squared-slotted dipole, meandered-slotted dipole, and straight-slotted dipole antennas, are introduced and implemented to increase the width of the on-chip antennas and thus the impedance bandwidth while meeting the DRC rules. All three topologies show better performance in terms of providing improved bandwidth. The straight-slotted technique is adopted as it offers less complexity and flexibility. The behavior of the impedances for different widths implemented by the straight-slotted topology has been analyzed in detail. A 6-strip straight-slotted dipole antenna results in an ultra-wide impedance bandwidth ranging from 76–262 GHz with a fractional bandwidth of 110% and a gain of −0.6 dBi at 159 GHz, while occupying a small silicon area of $567 μ m \times 112 μ m$ . To the best of the authors’ knowledge, this is the highest fractional bandwidth that is reported to date at these frequencies.

本文探讨了在亚 THz 频率范围内提高片上偶极子天线阻抗带宽的不同技术。增加偶极子天线的面积可显著改善带宽。然而，这违反了代工厂的设计规则检查（DRC）。我们引入并实施了各种拓扑结构，如方形槽偶极子、均线槽偶极子和直槽偶极子天线，以增加片上天线的宽度，从而提高阻抗带宽，同时满足 DRC 规则。这三种拓扑结构在提供更好的带宽方面都表现出了更好的性能。采用直槽技术是因为它的复杂性和灵活性较低。我们对直槽拓扑实现的不同宽度的阻抗行为进行了详细分析。6 条直槽偶极子天线实现了 76-262 GHz 的超宽阻抗带宽，分数带宽为 110%，在 159 GHz 时增益为 -0.6dBi，而占用的硅面积仅为 567μm×112μm 。据作者所知，这是迄今为止在这些频率下报告的最高分数带宽。

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引用次数: 0

An exponential variation based PSO for analog circuit sizing in constrained environment 基于指数变化的 PSO，适用于受限环境中的模拟电路选型

IF 3 3区计算机科学 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

Aeu-International Journal of Electronics and Communications

Pub Date : 2024-09-17 DOI: 10.1016/j.aeue.2024.155531

This work presents an Exponential Variation based Particle Swarm Optimization (EV-PSO) algorithm to improve the convergence rate and find an optimal solution to analog circuit optimization problems in a constrained-driven environment. Existing evolutionary algorithms have a lower convergence rate leading to higher design time. This work introduces two novel parameters, $ζ_{1}$ and $ζ_{2}$ , into the velocity update equation. These parameters dynamically vary with the number of iterations. The algorithm was implemented on the Python platform. The results have shown that, in comparison to the considered existing methods, the exponential variation of the parameters $ζ_{1}$ and $ζ_{2}$ in the proposed algorithms have a larger rate of convergence. The proposed EV-PSO has a convergence rate of 27 iterations, which is 57.8%, 65.38%, and 59.1% better than the conventional PSO, differential evolution (DE) and genetic algorithm (GA) respectively. The typical design obtained from the optimal solution is verified through the simulation using 45-nm CMOS technology. The optimal solution presented in this work meets the desired input specifications within the specified constrained environment.

本研究提出了一种基于指数变异的粒子群优化算法（EV-PSO），以提高收敛速度，并在约束驱动环境中找到模拟电路优化问题的最佳解决方案。现有的进化算法收敛速度较低，导致设计时间较长。这项研究在速度更新方程中引入了两个新参数：ζ1 和 ζ2。这些参数随迭代次数动态变化。该算法在 Python 平台上实现。结果表明，与现有方法相比，拟议算法中参数ζ1 和ζ2 的指数变化具有更大的收敛速度。所提出的 EV-PSO 的收敛速率为 27 次迭代，分别比传统 PSO、微分进化（DE）和遗传算法（GA）好 57.8%、65.38% 和 59.1%。通过使用 45 纳米 CMOS 技术进行仿真，验证了从最优解中获得的典型设计。这项工作中提出的最优解在指定的受限环境中满足了所需的输入规格。

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引用次数: 0