This work proposes a fast transient, dynamically biased cascoded flipped voltage follower low-dropout (LDO) regulator. The proposed LDO is constructed based on a single-stage error amplifier (EA) and a cascoded flipped voltage follower. The proposed error amplifier dynamically biases the CAFVF and enhances the transient and stability performance of the LDO regulator. This work uses three different feed-forward transconductors along with one miller and two feed-forward small compensatory capacitors. Two of these feed-forward transconductors and three small compensation capacitors generate two low-frequency left-half-plane (LHP) zeros in conjunction with the self-feed-forward path. These LHP zeros are unaffected by load conditions and provide consistent phase lead for all the load cases. Another feed-forward transconductor converts the load-dependent right-half-plane (RHP) Miller zero to an LHP zero. The load-dependent LHP zero appears closer to the unity gain frequency (UGF) for a lightly loaded LDO, improving its stability under light load situations. The proposed frequency compensation technique stabilizes the LDO for load currents ranging from 0 to , with a maximum load capacitor of . The proposed LDO is designed using UMC CMOS technology and implemented with the Cadence Virtuoso tool. With a maximum quiescent current of , the proposed LDO achieves a minimum good slew rate (SR) of and minimum unity gain frequency of , allowing it to settle faster with a settling time of . The reliability and robustness of the proposed LDO are verified using the process corners with an extreme temperature range and 200-point Monte Carlo simulations.
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