Design of Highly Reliable 14T and 16T SRAM Cells Combined With Layout Harden Technique

Abstract

The node upset may occur in the memory cell if the charged particle from cosmos rays or packaging materials strikes the integrated circuit. Radiation-hardened-by-design (RHBD) techniques introduce redundant transistors in the SRAM cell to improve its ability of recovering from the undesired node upset. However, the extra redundant transistors may increase the number of sensitive nodes in the SRAM cell, which decreases its capability of node-upset tolerance in turn. This work proposes an RHBD 14T SRAM cell and an RHBD 16T SRAM cell. Both the proposed SRAM cells only have two sensitive nodes. The proposed SRAM cells are able to recover from all the SNU cases. The layout harden technique is used to protect the proposed cells from SEMNU, and the blank of the hardened layout is reused so the proposed 14T and 16T SRAM cells consume the same area. Although the proposed cells have more transistors, the hardened layout areas of NS-10T/ PS-10T/ RHD-12T/ RHBD-10T/ RHBD-10T[VLSI]/ QUCCE-12T are respectively $1.78\times $ / $1.78\times $ / $1.83\times $ / $1.78\times $ / $1.78\times $ / $1.99\times $ larger than that of the proposed cells. The reason is that the layout harden technique is easier to be applied to the proposed cells because they only have two sensitive nodes.