Toward Efficient Asynchronous Circuits Design Flow Using Backward Delay Propagation Constraint

IF 2.8 2区 工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-07-01 DOI:10.1109/TVLSI.2024.3418769
Lingfeng Zhou;Shanlin Xiao;Huiyao Wang;Jinghai Wang;Zeyang Xu;Bohan Wang;Zhiyi Yu
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Abstract

In recent years, asynchronous circuits have gained attention in neural network chips and Internet of Things (IoT) due to their potential advantages of low power and high performance. However, design efficiency of asynchronous circuits remains low and faces challenges in large-scale applications because of the lack of electronic design automation (EDA) support. This article presents a new bundled-data (BD) asynchronous circuits’ design flow using traditional EDA tools, including a new backward delay propagation constraint (BDPC) method. In this method, control paths and data paths are analyzed together in a tightly coupled approach to improve the accuracy of static timing analysis (STA). Compared with other design flows, the proposed design flow and constraint method show significant advantages in aspects of STA accuracy, design efficiency, and design applicability, and solving the congestion issues of field-programmable gate array (FPGA) in a previous work. An asynchronous RISC-V processor was implemented to verify the method, with selective handshake technology to further reduce power. Compared with the synchronous processor, the asynchronous processor achieves a 17.4% power optimization on the TSMC 65-nm process and a 48.3% dynamic power savings on the FPGA while maintaining the same frequency and resource utilization.
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利用后向延迟传播约束实现高效异步电路设计流程
近年来,异步电路因其低功耗和高性能的潜在优势,在神经网络芯片和物联网(IoT)领域备受关注。然而,由于缺乏电子设计自动化(EDA)支持,异步电路的设计效率仍然较低,在大规模应用中面临挑战。本文介绍了一种使用传统 EDA 工具的新型捆绑数据(BD)异步电路设计流程,包括一种新的后向延迟传播约束(BDPC)方法。在这种方法中,控制路径和数据路径以紧密耦合的方式一起分析,以提高静态时序分析(STA)的准确性。与其他设计流程相比,所提出的设计流程和约束方法在静态时序分析的准确性、设计效率和设计适用性等方面都具有显著优势,并解决了之前工作中现场可编程门阵列(FPGA)的拥塞问题。为了验证该方法,我们使用选择性握手技术实现了异步 RISC-V 处理器,以进一步降低功耗。与同步处理器相比,异步处理器在台积电 65 纳米工艺上实现了 17.4% 的功耗优化,在 FPGA 上实现了 48.3% 的动态功耗节省,同时保持了相同的频率和资源利用率。
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来源期刊
CiteScore
6.40
自引率
7.10%
发文量
187
审稿时长
3.6 months
期刊介绍: The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.
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