Dynamic Neural Fields Accelerator Design for a Millimeter-Scale Tracking System

IF 2.8 2区工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-07-01 DOI:10.1109/TVLSI.2024.3416725

Yuyang Li;Vijay Shankaran Vivekanand;Rajkumar Kubendran;Inhee Lee

引用次数: 0

Abstract

This brief introduces a compact-size hardware accelerator for dynamic neural fields (DNF) used in object tracking. To address the substantial computational workload and memory occupancy associated with conventional DNFs, three key approaches are implemented: kernel size reduction and abstraction, the replacement of sigmoidal functions with comparison operations, and the approximation of rectangular-shaped objects. The design is realized in a 28-nm CMOS process, resulting in a layout with an area of 0.53 mm2. Simulation results demonstrate that the accelerator processes

$256 \times 256$

dynamic vision sensor (DVS) frames at 211 frames per second (fps), with a power consumption of 1.68 mW under such conditions.

查看原文

微信好友朋友圈 QQ好友复制链接

本刊更多论文

毫米级跟踪系统的动态神经场加速器设计

本简介介绍了用于物体跟踪的动态神经场（DNF）的紧凑型硬件加速器。为了解决与传统 DNF 相关的大量计算工作量和内存占用问题，我们采用了三种关键方法：减小内核大小并进行抽象、用比较运算取代正余弦函数以及近似矩形物体。设计采用 28 纳米 CMOS 工艺实现，布局面积为 0.53 平方毫米。仿真结果表明，该加速器能以每秒 211 帧的速度处理 256 次 256 美元的动态视觉传感器（DVS）帧，在这种条件下的功耗为 1.68 mW。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

求助全文

约1分钟内获得全文去求助

来源期刊

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 工程技术-工程：电子与电气

CiteScore

6.40

自引率

7.10%

发文量

187

审稿时长

3.6 months

期刊介绍： The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.

期刊最新文献

Table of Contents IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information IEEE Transactions on Very Large Scale Integration (VLSI) Systems Publication Information Table of Contents IEEE Transactions on Very Large Scale Integration (VLSI) Systems Publication Information