{"title":"Area Efficient 0.009-mm2 28.1-ppm/°C 11.3-MHz ALL-MOS Relaxation Oscillator","authors":"Joshua Adiel Wijaya;Poki Chen;Lucky Kumar Pradhan;Ahmad Shahid Bhatti;Seiji Kajihara","doi":"10.1109/TVLSI.2024.3416992","DOIUrl":null,"url":null,"abstract":"This article presents an ultrasmall area on-chip relaxation oscillator with low-temperature sensitivity. In this design, a virtual resistor mainly composed of a complementary to absolute temperature (CTAT) voltage reference circuit is implemented to replace the real resistor for efficient temperature compensation, which counterbalances the inherent proportional to absolute temperature (PTAT) property of the original relaxation circuit of the oscillator. The conventional capacitor is also replaced with a MOS capacitor to complete the ALL-MOS oscillator circuit with two prime advantages, one of which is larger capacitance to area density, and the other is better matching with critical MOSFETs. Implemented in a 0.18-\n<inline-formula> <tex-math>$\\mu $ </tex-math></inline-formula>\nm TSMC standard CMOS process, the proposed relaxation oscillator has achieved a temperature coefficient of 28.17 ppm/°C over the temperature range from \n<inline-formula> <tex-math>$- 25~^{\\circ }$ </tex-math></inline-formula>\nC to \n<inline-formula> <tex-math>$+ 125~^{\\circ }$ </tex-math></inline-formula>\nC at 11.39-MHz oscillation frequency. This circuit consumes \n<inline-formula> <tex-math>$243.1~\\mu $ </tex-math></inline-formula>\nW under 1.3-V power supply. Along with the abovementioned excellent performance, the oscillator achieves an ultrasmall core chip area of 0.009 mm2, which is almost one order less than most of the prior arts’ in the same process.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":null,"pages":null},"PeriodicalIF":2.8000,"publicationDate":"2024-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10576630/","RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
引用次数: 0
Abstract
This article presents an ultrasmall area on-chip relaxation oscillator with low-temperature sensitivity. In this design, a virtual resistor mainly composed of a complementary to absolute temperature (CTAT) voltage reference circuit is implemented to replace the real resistor for efficient temperature compensation, which counterbalances the inherent proportional to absolute temperature (PTAT) property of the original relaxation circuit of the oscillator. The conventional capacitor is also replaced with a MOS capacitor to complete the ALL-MOS oscillator circuit with two prime advantages, one of which is larger capacitance to area density, and the other is better matching with critical MOSFETs. Implemented in a 0.18-
$\mu $
m TSMC standard CMOS process, the proposed relaxation oscillator has achieved a temperature coefficient of 28.17 ppm/°C over the temperature range from
$- 25~^{\circ }$
C to
$+ 125~^{\circ }$
C at 11.39-MHz oscillation frequency. This circuit consumes
$243.1~\mu $
W under 1.3-V power supply. Along with the abovementioned excellent performance, the oscillator achieves an ultrasmall core chip area of 0.009 mm2, which is almost one order less than most of the prior arts’ in the same process.
期刊介绍:
The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society.
Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels.
To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.