An Energy-Efficient Low-Noise Neural Recording Circuit With Multi-Sampling SAR ADC

Abstract

This brief presents a low-power, high-precision neural recording circuit for closed-loop deep brain stimulation (DBS). It adopts a switched-capacitor (SC) low-pass filter (LPF) with the double sampling technique to efficiently attenuate high-frequency noise and signal with precise cut-off frequency. To improve power efficiency, this brief proposes a multi-sampling successive approximation register (SAR) analog-to-digital converter (ADC) for quantization. It synchronously samples LPF’s output, thus maximizing LPF’s power utilization. The single-channel prototype chip was fabricated in a 180 nm CMOS process. The neural recording channel consumes $31.98~ {\mu }\mathrm {W}$ from a 1.8-V supply. The proposed 11-bit multi-sampling SAR ADC features an ENOB of 10.38 bits at a sampling rate of 20.83 kS/s. The measured input-referred noise of the neural recording channel is $1.52~ {\mu }\mathrm {V_{rms}}$ for 1 Hz–300 Hz band and $1.96~ {\mu }\mathrm {V_{rms}}$ for 300 Hz–6.5 kHz band, respectively, promising a high precision for neural recording in closed-loop DBS systems.