Pub Date : 2025-03-31DOI: 10.1109/TCSII.2025.3550045
{"title":"IEEE Circuits and Systems Society Information","authors":"","doi":"10.1109/TCSII.2025.3550045","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3550045","url":null,"abstract":"","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 4","pages":"C3-C3"},"PeriodicalIF":4.0,"publicationDate":"2025-03-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10945817","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143740186","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-31DOI: 10.1109/TCSII.2025.3550043
{"title":"IEEE Transactions on Circuits and Systems--II: Express Briefs Publication Information","authors":"","doi":"10.1109/TCSII.2025.3550043","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3550043","url":null,"abstract":"","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 4","pages":"C2-C2"},"PeriodicalIF":4.0,"publicationDate":"2025-03-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10945880","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143740157","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-02-27DOI: 10.1109/TCSII.2025.3541469
{"title":"IEEE Transactions on Circuits and Systems--II: Express Briefs Publication Information","authors":"","doi":"10.1109/TCSII.2025.3541469","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3541469","url":null,"abstract":"","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 3","pages":"C2-C2"},"PeriodicalIF":4.0,"publicationDate":"2025-02-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10906742","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143512887","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-02-27DOI: 10.1109/TCSII.2025.3541471
{"title":"IEEE Circuits and Systems Society Information","authors":"","doi":"10.1109/TCSII.2025.3541471","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3541471","url":null,"abstract":"","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 3","pages":"C3-C3"},"PeriodicalIF":4.0,"publicationDate":"2025-02-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10906691","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143512890","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Due to the huge computational load, CNN-based super-resolution solutions are hard to be deployed on resource-constrained edge devices. In this brief, we proposed a Processing-in-Memory based SR accelerator (PIMSR) that leverages direct simple memory access operations to supersede intensive multiply-add in convolution operators, thus fundamentally improving the energy efficiency. To address the storage explosion problem, we presented an index reparameterized strategy for shrinking the memory requirement of LUT-based PIMSR framework by $19.58times $ . Furthermore, an address remapping design is putted forward to solve the access conflict in overlap configuration, which greatly boosts the efficiency of memory access. The prototype validation on low-end XC7A200T FPGA indicates that our design yields a new record of energy efficiency up to 671.61 Mpixels/J, over $5.36times $ higher than existing deep learning based image processors, with extremely low hardware costs.
{"title":"PIMSR: An Energy-Efficient Processing-in-Memory Accelerator for 60 FPS 4K Super-Resolution","authors":"Juntao Guan;Qinghui Guo;Huanan Li;Rui Lai;Ruixue Ding;Libo Qian;Zhangming Zhu","doi":"10.1109/TCSII.2025.3545466","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3545466","url":null,"abstract":"Due to the huge computational load, CNN-based super-resolution solutions are hard to be deployed on resource-constrained edge devices. In this brief, we proposed a Processing-in-Memory based SR accelerator (PIMSR) that leverages direct simple memory access operations to supersede intensive multiply-add in convolution operators, thus fundamentally improving the energy efficiency. To address the storage explosion problem, we presented an index reparameterized strategy for shrinking the memory requirement of LUT-based PIMSR framework by <inline-formula> <tex-math>$19.58times $ </tex-math></inline-formula>. Furthermore, an address remapping design is putted forward to solve the access conflict in overlap configuration, which greatly boosts the efficiency of memory access. The prototype validation on low-end XC7A200T FPGA indicates that our design yields a new record of energy efficiency up to 671.61 Mpixels/J, over <inline-formula> <tex-math>$5.36times $ </tex-math></inline-formula> higher than existing deep learning based image processors, with extremely low hardware costs.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 4","pages":"623-627"},"PeriodicalIF":4.0,"publicationDate":"2025-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143740384","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-02-24DOI: 10.1109/TCSII.2025.3545303
Venakata Sitaraman Puram;Vamsi Krishna Velidi;Arijit De
In the above paper (Feng et al., 2020) design of dual band branch-line couplers with short/open-ended stubs was presented. However, there are some major discrepancies & mistakes observed in the design equations and plots as well. For the case of dual band design using open-circuited stubs, it is found that the basic operation of the coupler is lost, where the through port behaves as isolated port and vice versa when attempted to design using circuit simulators with the impedances provided in (Feng et al., 2020). Here, corrected versions for the band ratio versus impedance plots for both dual-band couplers with short-ended and open-ended stubs are provided. Further, the correct design equations are derived and accordingly the correct simulation S-parameter plots for the dual-band couplers with open-ended stubs, along with corrected k values are given. Moreover, other minor typo errors to be noted for better readability for the research community are provided.
{"title":"Comments on “Dual-Band Branch-Line Couplers With Short/Open-Ended Stubs”","authors":"Venakata Sitaraman Puram;Vamsi Krishna Velidi;Arijit De","doi":"10.1109/TCSII.2025.3545303","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3545303","url":null,"abstract":"In the above paper (Feng et al., 2020) design of dual band branch-line couplers with short/open-ended stubs was presented. However, there are some major discrepancies & mistakes observed in the design equations and plots as well. For the case of dual band design using open-circuited stubs, it is found that the basic operation of the coupler is lost, where the through port behaves as isolated port and vice versa when attempted to design using circuit simulators with the impedances provided in (Feng et al., 2020). Here, corrected versions for the band ratio versus impedance plots for both dual-band couplers with short-ended and open-ended stubs are provided. Further, the correct design equations are derived and accordingly the correct simulation S-parameter plots for the dual-band couplers with open-ended stubs, along with corrected k values are given. Moreover, other minor typo errors to be noted for better readability for the research community are provided.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 4","pages":"564-567"},"PeriodicalIF":4.0,"publicationDate":"2025-02-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143740188","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-02-21DOI: 10.1109/TCSII.2025.3544818
Yongqian Wang;Zhenghao Ni;Jing Wang;Ju H. Park;Hao Shen
This brief addresses the problem of asynchronous reduced-order filtering for Markov jump systems. The communication between the reduced-order filters and the systems is transmitted through the network. On the one hand, quantization is considered to save network resources; on the other hand, due to the measurement may not be perfect, the system information is a hidden component (i.e., it possesses inaccessibility), therefore reduced-order filters are designed by using the hidden Markov model. Then, the random stability of the plant is guaranteed by a set of conditions derived according to Lyapunov theory. Subsequently, the gains of the designed filters are obtained through decoupling. Finally, the effectiveness of the proposed approach in this brief is confirmed by utilizing a pulse-width-modulation-driven boost converter.
{"title":"Asynchronous Reduced-Order Filtering for Markov Jump Systems and its Application in PWM Circuits","authors":"Yongqian Wang;Zhenghao Ni;Jing Wang;Ju H. Park;Hao Shen","doi":"10.1109/TCSII.2025.3544818","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3544818","url":null,"abstract":"This brief addresses the problem of asynchronous reduced-order filtering for Markov jump systems. The communication between the reduced-order filters and the systems is transmitted through the network. On the one hand, quantization is considered to save network resources; on the other hand, due to the measurement may not be perfect, the system information is a hidden component (i.e., it possesses inaccessibility), therefore reduced-order filters are designed by using the hidden Markov model. Then, the random stability of the plant is guaranteed by a set of conditions derived according to Lyapunov theory. Subsequently, the gains of the designed filters are obtained through decoupling. Finally, the effectiveness of the proposed approach in this brief is confirmed by utilizing a pulse-width-modulation-driven boost converter.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 4","pages":"598-602"},"PeriodicalIF":4.0,"publicationDate":"2025-02-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143740335","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this brief, a ring-oscillator-based true random number generator (RO-TRNG) is presented with an energy-efficient on-chip module for temporal thresholding of the accumulated jitter noise. The need of power-hungry reference ring oscillator (RO) for frequency collapse detection in previous implementation can be completely removed. In addition, by setting the RO-TRNG’s enable signal adaptively according to the output of the proposed jitter accumulation thresholding (JAT) module, the redundant oscillations in most cycles of the prior art can be fully eliminated, leading to significant energy saving per each TRNG bit. Based on a 65-nm 1.2 V standard CMOS process, the fabricated TRNG chips feature an ultra-compact silicon area of 149 K$F^{2}$ . Meanwhile, a high energy efficiency of 1.46 pJ/bit is achieved for the prototype chips operated under a supply voltage of 1.0 V and an overall throughput of 44.7 Mbps. High randomness of the fabricated TRNG chips is well validated by using both National Institute of Standards and Technology (NIST) and autocorrelation function (ACF) test tools. Moreover, high Shannon entropy values over 0.999998 are observed for the TRNG chips operated under an industrial temperature range of −40°C~125°C and a supply voltage range of 1.0 V~1.4 V, showing excellent tolerance to the process-voltage-temperature (PVT) variations.
{"title":"A 1.46-pJ/bit, 149-KF² RO TRNG Based on Reference-RO-Free Thresholding of Jitter Accumulation","authors":"Haibiao Zuo;Qingsen Zhuang;Jiacheng Hao;Haochen Zhong;Xiaojin Zhao","doi":"10.1109/TCSII.2025.3543628","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3543628","url":null,"abstract":"In this brief, a ring-oscillator-based true random number generator (RO-TRNG) is presented with an energy-efficient on-chip module for temporal thresholding of the accumulated jitter noise. The need of power-hungry reference ring oscillator (RO) for frequency collapse detection in previous implementation can be completely removed. In addition, by setting the RO-TRNG’s enable signal adaptively according to the output of the proposed jitter accumulation thresholding (JAT) module, the redundant oscillations in most cycles of the prior art can be fully eliminated, leading to significant energy saving per each TRNG bit. Based on a 65-nm 1.2 V standard CMOS process, the fabricated TRNG chips feature an ultra-compact silicon area of 149 K<inline-formula> <tex-math>$F^{2}$ </tex-math></inline-formula>. Meanwhile, a high energy efficiency of 1.46 pJ/bit is achieved for the prototype chips operated under a supply voltage of 1.0 V and an overall throughput of 44.7 Mbps. High randomness of the fabricated TRNG chips is well validated by using both National Institute of Standards and Technology (NIST) and autocorrelation function (ACF) test tools. Moreover, high Shannon entropy values over 0.999998 are observed for the TRNG chips operated under an industrial temperature range of −40°C~125°C and a supply voltage range of 1.0 V~1.4 V, showing excellent tolerance to the process-voltage-temperature (PVT) variations.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 4","pages":"618-622"},"PeriodicalIF":4.0,"publicationDate":"2025-02-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143740187","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-02-18DOI: 10.1109/TCSII.2025.3543326
Xin-Yu Shih;Hsi-Cheng Chen;Xin-Liang Hung
In this brief, we propose a first system chip architecture of 4-splitting tree-structure-based K-means clustering trainer and classifier. It mainly aims to efficiently detect cybersecurity attacks in the emerging AI-driven world. In addition, we also propose three design techniques to elaborate our chip, featuring a low-latency property in both training and classification aspects. Our developed architecture is first validated with the Xilinx FPGA platform. Furthermore, it is implemented in ASIC and well-verified with five representative cybersecurity-related datasets. The total core area with TSMC 40nm low-Vt CMOS technology only occupies 0.44 um2, maximally operating at 434.78 MHz and possessing a maximum classification throughput of 3.48 GBps on chip. In comparison, the speed-up ratio of training and classification is up to 9.33 and 8.73 times, respectively, successfully delivering a low-latency characteristic.
{"title":"Design and Hardware Implementation of Low-Latency 4-Splitting Tree-Structure-Based K-Means Clustering Trainer and Classifier Chip for Detecting Cybersecurity Attacks","authors":"Xin-Yu Shih;Hsi-Cheng Chen;Xin-Liang Hung","doi":"10.1109/TCSII.2025.3543326","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3543326","url":null,"abstract":"In this brief, we propose a first system chip architecture of 4-splitting tree-structure-based K-means clustering trainer and classifier. It mainly aims to efficiently detect cybersecurity attacks in the emerging AI-driven world. In addition, we also propose three design techniques to elaborate our chip, featuring a low-latency property in both training and classification aspects. Our developed architecture is first validated with the Xilinx FPGA platform. Furthermore, it is implemented in ASIC and well-verified with five representative cybersecurity-related datasets. The total core area with TSMC 40nm low-Vt CMOS technology only occupies 0.44 um2, maximally operating at 434.78 MHz and possessing a maximum classification throughput of 3.48 GBps on chip. In comparison, the speed-up ratio of training and classification is up to 9.33 and 8.73 times, respectively, successfully delivering a low-latency characteristic.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 4","pages":"613-617"},"PeriodicalIF":4.0,"publicationDate":"2025-02-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143740146","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-02-18DOI: 10.1109/TCSII.2025.3543306
Junhyeop Kim;Juhui Jeong;Junghwan Han
This brief presents a cryogenic complementary metal-oxide-semiconductor (CMOS) active mixer designed to achieve low-noise and low-power characteristics at cryogenic temperatures. The proposed design employs a transformer-based current-bleeding (CB) technique that further enhances both the conversion gain and noise performance of the mixer when compared to the conventional CB approaches. Implemented as a double-balanced active mixer, the design was fabricated using a 65-nm CMOS process and validated across the 4–8 GHz frequency range under both cryogenic and room temperatures.
{"title":"Cryogenic CMOS Active Mixer Employing Transformer-Based Current-Bleeding Technique","authors":"Junhyeop Kim;Juhui Jeong;Junghwan Han","doi":"10.1109/TCSII.2025.3543306","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3543306","url":null,"abstract":"This brief presents a cryogenic complementary metal-oxide-semiconductor (CMOS) active mixer designed to achieve low-noise and low-power characteristics at cryogenic temperatures. The proposed design employs a transformer-based current-bleeding (CB) technique that further enhances both the conversion gain and noise performance of the mixer when compared to the conventional CB approaches. Implemented as a double-balanced active mixer, the design was fabricated using a 65-nm CMOS process and validated across the 4–8 GHz frequency range under both cryogenic and room temperatures.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 4","pages":"568-572"},"PeriodicalIF":4.0,"publicationDate":"2025-02-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143740154","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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