Pub Date : 2026-01-30DOI: 10.1109/TCSII.2026.3655135
{"title":"IEEE Circuits and Systems Society Information","authors":"","doi":"10.1109/TCSII.2026.3655135","DOIUrl":"https://doi.org/10.1109/TCSII.2026.3655135","url":null,"abstract":"","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 2","pages":"C3-C3"},"PeriodicalIF":4.9,"publicationDate":"2026-01-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11369806","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146082048","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-01-06DOI: 10.1109/TCSII.2025.3641493
{"title":"IEEE Circuits and Systems Society Information","authors":"","doi":"10.1109/TCSII.2025.3641493","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3641493","url":null,"abstract":"","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 1","pages":"C3-C3"},"PeriodicalIF":4.9,"publicationDate":"2026-01-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11330180","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145904304","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-01-06DOI: 10.1109/TCSII.2025.3641491
{"title":"IEEE Transactions on Circuits and Systems--II: Express Briefs Publication Information","authors":"","doi":"10.1109/TCSII.2025.3641491","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3641491","url":null,"abstract":"","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 1","pages":"C2-C2"},"PeriodicalIF":4.9,"publicationDate":"2026-01-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11330183","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145904325","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-01-06DOI: 10.1109/TCSII.2025.3633439
Edoardo Bonizzoni
{"title":"Incoming Editorial","authors":"Edoardo Bonizzoni","doi":"10.1109/TCSII.2025.3633439","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3633439","url":null,"abstract":"","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 1","pages":"1-2"},"PeriodicalIF":4.9,"publicationDate":"2026-01-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11330184","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145904295","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-22DOI: 10.1109/TCSII.2025.3646688
Zibin Guo;Yulong Gui;Yanzhao Ma
This brief presents an all-in-one isolated DC-DC converter combines a primary flyback controller, secondary synchronous rectifier and digital isolator on a single chip. The converter adopts quasi-resonant (QR) peak current mode control with valley-hysteresis-locking (VHL) method. The adaptive peak current and VHL techniques could prevent sudden frequency hopping at some load point. Additionally, a down-hill detection method in the valley detector ensures accurate valley switching operation. With these proposed techniques, the converter could realize quasi-resonant under different load conditions. The chip has been fabricated with a $0.18~mu $ m BCD process, and the primary and secondary control chips occupy the area of 1.04 mm2 and 0.62 mm2, respectively. The converter delivers 12 V output with a maximum current of 2 A, achieving a peak efficiency of 91.5%.
{"title":"A 24-W 91.5% Peak Efficiency All-in-One Dual-Loop Controlled Quasi-Resonant Isolated DC–DC Converter With Adaptive Peak Current and Valley-Hysteresis-Locking Techniques","authors":"Zibin Guo;Yulong Gui;Yanzhao Ma","doi":"10.1109/TCSII.2025.3646688","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3646688","url":null,"abstract":"This brief presents an all-in-one isolated DC-DC converter combines a primary flyback controller, secondary synchronous rectifier and digital isolator on a single chip. The converter adopts quasi-resonant (QR) peak current mode control with valley-hysteresis-locking (VHL) method. The adaptive peak current and VHL techniques could prevent sudden frequency hopping at some load point. Additionally, a down-hill detection method in the valley detector ensures accurate valley switching operation. With these proposed techniques, the converter could realize quasi-resonant under different load conditions. The chip has been fabricated with a <inline-formula> <tex-math>$0.18~mu $ </tex-math></inline-formula>m BCD process, and the primary and secondary control chips occupy the area of 1.04 mm<sup>2</sup> and 0.62 mm<sup>2</sup>, respectively. The converter delivers 12 V output with a maximum current of 2 A, achieving a peak efficiency of 91.5%.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 2","pages":"228-232"},"PeriodicalIF":4.9,"publicationDate":"2025-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146082114","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Efficient AC–DC interfaces are essential for low-power energy harvesters to power intracardiac leadless pacemakers (ICLPs) reliably. For the front-end circuitry, selecting a diode that minimizes both conduction and leakage losses under specified operating conditions is challenging, as the forward voltage drop and reverse leakage current cannot be simultaneously reduced due to the device’s inherent physics. This brief presents a machine learning framework that predicts the DC output of diode-based AC-DC interfaces directly from specific voltage-current (V-I) characteristic points of the diodes and descriptive features of the excitation waveform. A physics-informed surrogate model is trained on SPICE-simulated data of rectifiers driven by experimentally captured cardiac harvester waveforms. Hardware validation with printed-circuit rectifiers powered by the same harvester source exhibits an average error of 0.03 V between prediction and measurement, matching the performance observed on the synthetic set and demonstrating robust generalization to real-world applications. This data-driven approach offers an instant, datasheet-only diode screening without circuit-level evaluation and can be integrated into automated multi-objective optimization flows for the design of low-power energy harvester AC–DC interfaces.
{"title":"Physics-Informed Surrogate Neural Network for Optimizing Diode-Based Interfaces in Leadless Pacemaker Energy Harvesting","authors":"Qirui Hua;Majid Khazaee;Ali Asghar Enkeshafi;Ming Shen;Sam Riahi;Alireza Rezaniakolaei","doi":"10.1109/TCSII.2025.3641701","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3641701","url":null,"abstract":"Efficient AC–DC interfaces are essential for low-power energy harvesters to power intracardiac leadless pacemakers (ICLPs) reliably. For the front-end circuitry, selecting a diode that minimizes both conduction and leakage losses under specified operating conditions is challenging, as the forward voltage drop and reverse leakage current cannot be simultaneously reduced due to the device’s inherent physics. This brief presents a machine learning framework that predicts the DC output of diode-based AC-DC interfaces directly from specific voltage-current (V-I) characteristic points of the diodes and descriptive features of the excitation waveform. A physics-informed surrogate model is trained on SPICE-simulated data of rectifiers driven by experimentally captured cardiac harvester waveforms. Hardware validation with printed-circuit rectifiers powered by the same harvester source exhibits an average error of 0.03 V between prediction and measurement, matching the performance observed on the synthetic set and demonstrating robust generalization to real-world applications. This data-driven approach offers an instant, datasheet-only diode screening without circuit-level evaluation and can be integrated into automated multi-objective optimization flows for the design of low-power energy harvester AC–DC interfaces.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 2","pages":"223-227"},"PeriodicalIF":4.9,"publicationDate":"2025-12-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146082227","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-04DOI: 10.1109/TCSII.2025.3640485
{"title":"2025 Index IEEE Transactions on Circuits and Systems--II","authors":"","doi":"10.1109/TCSII.2025.3640485","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3640485","url":null,"abstract":"","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 12","pages":"1-102"},"PeriodicalIF":4.9,"publicationDate":"2025-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11278479","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145674664","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-01DOI: 10.1109/TCSII.2025.3638907
Nengxu Zhu;Yiting Zhang;Zenglong Zhao;Fanyi Meng
This brief presents a compact DC-to-6 GHz single-pole double-throw (SPDT) switch utilizing embedded RLC resonator technology. Building upon the traditional series-shunt RCstructure, an inductor is incorporated between the series and shunt transistors, working in conjunction with the port-matching inductors to achieve broadband low-loss characteristics in the through mode. In the isolation mode, the structure forms an RLC resonator to enhance isolation. To improve linearity, quadruple-stacked transistors are employed for both the series and shunt-switching transistors. Fabricated using the SMIC $0.13~mu $ m CMOS SOI process, the measurement results demonstrate that the chip achieves an isolation of >50 dB across the DC-to-6 GHz range, with an insertion loss of only 0.4–1.2 dB and an input power at 1 dB compression point (IP1dB) of 20 dBm at 5 GHz. The core area of the chip is only 0.06 mm2.
{"title":"Design of a Compact Wideband SPDT Switch With High Isolation for Sub-6 GHz Applications","authors":"Nengxu Zhu;Yiting Zhang;Zenglong Zhao;Fanyi Meng","doi":"10.1109/TCSII.2025.3638907","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3638907","url":null,"abstract":"This brief presents a compact DC-to-6 GHz single-pole double-throw (SPDT) switch utilizing embedded <italic>RLC</i> resonator technology. Building upon the traditional series-shunt <italic>RC</i>structure, an inductor is incorporated between the series and shunt transistors, working in conjunction with the port-matching inductors to achieve broadband low-loss characteristics in the through mode. In the isolation mode, the structure forms an <italic>RLC</i> resonator to enhance isolation. To improve linearity, quadruple-stacked transistors are employed for both the series and shunt-switching transistors. Fabricated using the SMIC <inline-formula> <tex-math>$0.13~mu $ </tex-math></inline-formula>m CMOS SOI process, the measurement results demonstrate that the chip achieves an isolation of >50 dB across the DC-to-6 GHz range, with an insertion loss of only 0.4–1.2 dB and an input power at 1 dB compression point (IP<sub>1dB</sub>) of 20 dBm at 5 GHz. The core area of the chip is only 0.06 mm<sup>2</sup>.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 1","pages":"43-47"},"PeriodicalIF":4.9,"publicationDate":"2025-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145904315","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-26DOI: 10.1109/TCSII.2025.3637298
Gaoyuan Zhao;Xiangyu Meng;Pengfei Bai;Baoyong Chi
This brief presents a 5-bit CMOS attenuator employing an NMOS on-resistance self-locking technique to address temperature drift and process variations in millimeter-wave phased arrays. Unlike conventional polysilicon resistor networks, the proposed design features an all-NMOS attenuation network operating in the deep linear region, leveraging transistor parasitic capacitance for intrinsic phase compensation. A closed-loop feedback mechanism dynamically stabilizes on-resistance by real-time gate bias adjustment, eliminating external tuning while suppressing PVT variations across DC–30 GHz. Measurement results demonstrate 0.46 dB RMS amplitude error and 1.77° RMS phase error, with cross-chip comparisons revealing process variation tolerance: inter-chip discrepancies remain below 0.06 dB (gain) and 1.36° (phase). The self-locking loop achieves fully automatic impedance stabilization with $868~mu $ W power consumption and 0.0148 mm2 core area in 65 nm CMOS.
{"title":"A DC-to-30 GHz NMOS Attenuator With Constant MOSFET On-Resistance","authors":"Gaoyuan Zhao;Xiangyu Meng;Pengfei Bai;Baoyong Chi","doi":"10.1109/TCSII.2025.3637298","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3637298","url":null,"abstract":"This brief presents a 5-bit CMOS attenuator employing an NMOS on-resistance self-locking technique to address temperature drift and process variations in millimeter-wave phased arrays. Unlike conventional polysilicon resistor networks, the proposed design features an all-NMOS attenuation network operating in the deep linear region, leveraging transistor parasitic capacitance for intrinsic phase compensation. A closed-loop feedback mechanism dynamically stabilizes on-resistance by real-time gate bias adjustment, eliminating external tuning while suppressing PVT variations across DC–30 GHz. Measurement results demonstrate 0.46 dB RMS amplitude error and 1.77° RMS phase error, with cross-chip comparisons revealing process variation tolerance: inter-chip discrepancies remain below 0.06 dB (gain) and 1.36° (phase). The self-locking loop achieves fully automatic impedance stabilization with <inline-formula> <tex-math>$868~mu $ </tex-math></inline-formula>W power consumption and 0.0148 mm<sup>2</sup> core area in 65 nm CMOS.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 1","pages":"33-37"},"PeriodicalIF":4.9,"publicationDate":"2025-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145904309","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This brief presents a 25-Mbps 4-amplitude-shift-keying (4-ASK) receiver front-end (RFE) for biomedical data telemetry via a series-resonant capacitive link. The RFE incorporates low-power clock and data recovery (CDR) circuitry for synchronization in which a novel highly linear transconductance ($G_{mathbf {m}}$ ) cell is employed in the phase detector (PD) to mitigate any possible error decisions while comparing the phase difference between the input and feedback signals. The proposed RFE is fabricated in 65 nm 1P8M standard CMOS, the core circuit occupies 0.11 mm${}^{mathbf {2}}$ , and consumes 2.9 mA from 1 V. While conducting $ex ~vivo$ measurements using beef tissue and a series-resonant capacitive link, the proposed RFE is capable of processing 4-ASK data patterns up to 25 Mbps with bit error rate (BER) less than $10^{mathbf {-3}}$ and total jitter of ~42 ns.
{"title":"A 25-Mb/s 4-ASK Receiver Front-End in 65-nm CMOS for Biomedical Data Telemetry via a Capacitive Link","authors":"Hossein Yaghobi;Mohammad Mobaraki;Pedram Mohseni;Hossein Miri Lavasani","doi":"10.1109/TCSII.2025.3637697","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3637697","url":null,"abstract":"This brief presents a 25-Mbps 4-amplitude-shift-keying (4-ASK) receiver front-end (RFE) for biomedical data telemetry via a series-resonant capacitive link. The RFE incorporates low-power clock and data recovery (CDR) circuitry for synchronization in which a novel highly linear transconductance (<inline-formula> <tex-math>$G_{mathbf {m}}$ </tex-math></inline-formula>) cell is employed in the phase detector (PD) to mitigate any possible error decisions while comparing the phase difference between the input and feedback signals. The proposed RFE is fabricated in 65 nm 1P8M standard CMOS, the core circuit occupies 0.11 mm<inline-formula> <tex-math>${}^{mathbf {2}}$ </tex-math></inline-formula>, and consumes 2.9 mA from 1 V. While conducting <inline-formula> <tex-math>$ex ~vivo$ </tex-math></inline-formula> measurements using beef tissue and a series-resonant capacitive link, the proposed RFE is capable of processing 4-ASK data patterns up to 25 Mbps with bit error rate (BER) less than <inline-formula> <tex-math>$10^{mathbf {-3}}$ </tex-math></inline-formula> and total jitter of ~42 ns.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 1","pages":"38-42"},"PeriodicalIF":4.9,"publicationDate":"2025-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145904345","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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