Pub Date : 2025-01-08DOI: 10.1109/TCSII.2025.3527324
{"title":"2024 Index IEEE Transactions on Circuits and Systems II: Express Briefs Vol. 71","authors":"","doi":"10.1109/TCSII.2025.3527324","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3527324","url":null,"abstract":"","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"71 12","pages":"1-187"},"PeriodicalIF":4.0,"publicationDate":"2025-01-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10834408","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142937907","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-24DOI: 10.1109/TCSII.2024.3513179
{"title":"IEEE Circuits and Systems Society Information","authors":"","doi":"10.1109/TCSII.2024.3513179","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3513179","url":null,"abstract":"","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"C3-C3"},"PeriodicalIF":4.0,"publicationDate":"2024-12-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10814108","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142890218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-24DOI: 10.1109/TCSII.2024.3513175
{"title":"IEEE Transactions on Circuits and Systems--II: Express Briefs Publication Information","authors":"","doi":"10.1109/TCSII.2024.3513175","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3513175","url":null,"abstract":"","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"C2-C2"},"PeriodicalIF":4.0,"publicationDate":"2024-12-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10814107","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142880361","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-27DOI: 10.1109/TCSII.2024.3507175
Insu Han;Hanjung Lee;Seong-Mo Moon;Inchan Ju
This brief presents a dual power mode (DPM) Q/V-band SiGe HBT cascode power amplifier (PA) for emerging very low-earth-orbit (VLEO) satellite communication (SATCOM). A novel reconfigurable four-way Wilkinson power combiner balun (WPCB) is proposed, where built-in a collector-to-base (CB) junction of upper HBTs in a SiGe HBT cascode is reconfigured to either reverse- or forward-biased to support high power (HP) or low power (LP) modes of the PA, respectively. This DPM scheme neither requires any lossy series switch at the PA output nor dual power supplies, which improves PA efficiency at power back off (PBO) and reduces system complexity. The DPM PA prototype is fabricated in 0.13 $mu $ m SiGe HBT BiCMOS. For HP/LP modes, the PA attains measured peak output power (POUT) and peak power added efficiency (PAE) 23.3/18.7 dBm and 30.4/25.8% at 45.0 GHz, respectively, demonstrating its DPM capability. For HP/LP modes at 45 GHz, it delivers linear $P_{mathrm { OUT}}$ (PAVG) of 17.0/11.8 dBm with average PAE (PAEAVG) of 17.7/13.0% at 250MHz symbol rate DVB-S2X 64 ASPK modulation signal.
{"title":"A Dual Power Mode Q/V-Band SiGe HBT Cascode Power Amplifier With a Novel Reconfigurable Four-Way Wilkinson Power Combiner Balun","authors":"Insu Han;Hanjung Lee;Seong-Mo Moon;Inchan Ju","doi":"10.1109/TCSII.2024.3507175","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3507175","url":null,"abstract":"This brief presents a dual power mode (DPM) Q/V-band SiGe HBT cascode power amplifier (PA) for emerging very low-earth-orbit (VLEO) satellite communication (SATCOM). A novel reconfigurable four-way Wilkinson power combiner balun (WPCB) is proposed, where built-in a collector-to-base (CB) junction of upper HBTs in a SiGe HBT cascode is reconfigured to either reverse- or forward-biased to support high power (HP) or low power (LP) modes of the PA, respectively. This DPM scheme neither requires any lossy series switch at the PA output nor dual power supplies, which improves PA efficiency at power back off (PBO) and reduces system complexity. The DPM PA prototype is fabricated in 0.13 \u0000<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>\u0000m SiGe HBT BiCMOS. For HP/LP modes, the PA attains measured peak output power (POUT) and peak power added efficiency (PAE) 23.3/18.7 dBm and 30.4/25.8% at 45.0 GHz, respectively, demonstrating its DPM capability. For HP/LP modes at 45 GHz, it delivers linear \u0000<inline-formula> <tex-math>$P_{mathrm { OUT}}$ </tex-math></inline-formula>\u0000 (PAVG) of 17.0/11.8 dBm with average PAE (PAEAVG) of 17.7/13.0% at 250MHz symbol rate DVB-S2X 64 ASPK modulation signal.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"168-172"},"PeriodicalIF":4.0,"publicationDate":"2024-11-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142880365","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-25DOI: 10.1109/TCSII.2024.3490935
{"title":"IEEE Transactions on Circuits and Systems--II: Express Briefs Publication Information","authors":"","doi":"10.1109/TCSII.2024.3490935","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3490935","url":null,"abstract":"","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"71 12","pages":"C2-C2"},"PeriodicalIF":4.0,"publicationDate":"2024-11-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10767316","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142713845","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-25DOI: 10.1109/TCSII.2024.3505153
Jing Xie;Han Su;Dong Yang;Ben Niu
This brief concentrates on the problem of $H_{infty }$ anti-disturbance bumpless transfer control (ADBTC) of switched affine systems (SASs) with multiple types of disturbances. The $H_{infty }$ ADBTC strategy is put forward to achieve the bumpless transfer (BT) performance and the anti-disturbance performance, simultaneously. First, a more general switched affine disturbance observer is designed to estimate the external disturbances generated from the external SASs. Secondly, a novel BT performance constraint containing the system state, the disturbance observer state, and the affine terms is proposed to suppress the control bumps. Thirdly, a switched anti-disturbance BT controller and a state-dependent switching law are constructed. Then a solvable condition for the $H_{infty }$ ADBTC problem of SASs is derived. Finally, the proposed control scheme is validated by an example of a circuit model.
{"title":"H∞ Anti-Disturbance Bumpless Transfer Control for Switched Affine Systems With Its Application to a Circuit Model","authors":"Jing Xie;Han Su;Dong Yang;Ben Niu","doi":"10.1109/TCSII.2024.3505153","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3505153","url":null,"abstract":"This brief concentrates on the problem of \u0000<inline-formula> <tex-math>$H_{infty }$ </tex-math></inline-formula>\u0000 anti-disturbance bumpless transfer control (ADBTC) of switched affine systems (SASs) with multiple types of disturbances. The \u0000<inline-formula> <tex-math>$H_{infty }$ </tex-math></inline-formula>\u0000 ADBTC strategy is put forward to achieve the bumpless transfer (BT) performance and the anti-disturbance performance, simultaneously. First, a more general switched affine disturbance observer is designed to estimate the external disturbances generated from the external SASs. Secondly, a novel BT performance constraint containing the system state, the disturbance observer state, and the affine terms is proposed to suppress the control bumps. Thirdly, a switched anti-disturbance BT controller and a state-dependent switching law are constructed. Then a solvable condition for the \u0000<inline-formula> <tex-math>$H_{infty }$ </tex-math></inline-formula>\u0000 ADBTC problem of SASs is derived. Finally, the proposed control scheme is validated by an example of a circuit model.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"238-242"},"PeriodicalIF":4.0,"publicationDate":"2024-11-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142880422","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-25DOI: 10.1109/TCSII.2024.3501113
{"title":"TechRxiv: Share Your Preprint Research with the World!","authors":"","doi":"10.1109/TCSII.2024.3501113","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3501113","url":null,"abstract":"","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"71 12","pages":"5069-5069"},"PeriodicalIF":4.0,"publicationDate":"2024-11-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10767257","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142757828","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-25DOI: 10.1109/TCSII.2024.3490937
{"title":"IEEE Circuits and Systems Society Information","authors":"","doi":"10.1109/TCSII.2024.3490937","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3490937","url":null,"abstract":"","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"71 12","pages":"C3-C3"},"PeriodicalIF":4.0,"publicationDate":"2024-11-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10767254","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142757820","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-21DOI: 10.1109/TCSII.2024.3503771
Luhua Lin;Bowen Wang;Woogeun Rhee;Zhihua Wang
This brief describes an ultra-wideband (UWB) transceiver architecture that employs a frequency-hopping code-division multiple-access (FH-CDMA) scheme for secure multi-sensor connectivity with up to 18-channel capacity. By using distinct frequency-hopping (FH) patterns based on m-sequence, quantitative analysis and simulation results show that the FH-CDMA UWB system can support up to 18 users simultaneously sharing the same transmission band. The duty cycle control of a carrier signal for each FH cycle enables the transmitter to perform baseband clock synchronization with nano-second resolution. A prototype 7.5-GHz UWB transceiver is implemented in 65-nm CMOS. With the FH enabled, the transmitter meets the UWB spectrum mask. The receiver achieves a sensitivity of –91 dBm at 25 kb/s and exhibits <1-dB degradation when three users transmit signals simultaneously.
{"title":"A 7.5-GHz Frequency-Hopping CDMA UWB Transceiver for Secure Multi-Sensor Connectivity","authors":"Luhua Lin;Bowen Wang;Woogeun Rhee;Zhihua Wang","doi":"10.1109/TCSII.2024.3503771","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3503771","url":null,"abstract":"This brief describes an ultra-wideband (UWB) transceiver architecture that employs a frequency-hopping code-division multiple-access (FH-CDMA) scheme for secure multi-sensor connectivity with up to 18-channel capacity. By using distinct frequency-hopping (FH) patterns based on m-sequence, quantitative analysis and simulation results show that the FH-CDMA UWB system can support up to 18 users simultaneously sharing the same transmission band. The duty cycle control of a carrier signal for each FH cycle enables the transmitter to perform baseband clock synchronization with nano-second resolution. A prototype 7.5-GHz UWB transceiver is implemented in 65-nm CMOS. With the FH enabled, the transmitter meets the UWB spectrum mask. The receiver achieves a sensitivity of –91 dBm at 25 kb/s and exhibits <1-dB degradation when three users transmit signals simultaneously.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"163-167"},"PeriodicalIF":4.0,"publicationDate":"2024-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142880424","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-21DOI: 10.1109/TCSII.2024.3503659
Lijuan Wang;Yizhu Shen;Yun Qian;Yifan Ding;Sanming Hu
This brief proposes a low noise amplifier (LNA) with high gain at 220 GHz in bulk CMOS process. A $G_{max }$ -core is employed to simultaneously realize noise and power matching as well as provide high gain. A segmented design methodology for LNAs in terahertz band is employed to trade-off gain and noise. Incorporating the $G_{max }$ -core with design methodology, a 220 GHz LNA is designed with balanced noise and gain performance. Fabricated using 40nm bulk CMOS process, measurement results reveal a minimum noise figure of 9.7 dB, a maximum gain of 24.8 dB between 214-225 GHz, and a saturated output power of −0.58 dBm at 220 GHz, while consuming only 36.9 mW. The LNA occupies a compact total area of 0.2 mm2, with a core area of 0.047 mm2. To the best of the authors’ knowledge, this represents the lowest noise figure achieved by LNA above 200 GHz using bulk CMOS technology.
{"title":"A 220-GHz LNA With 9.7-dB Noise Figure and 24.6-dB Gain in 40-nm Bulk CMOS","authors":"Lijuan Wang;Yizhu Shen;Yun Qian;Yifan Ding;Sanming Hu","doi":"10.1109/TCSII.2024.3503659","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3503659","url":null,"abstract":"This brief proposes a low noise amplifier (LNA) with high gain at 220 GHz in bulk CMOS process. A \u0000<inline-formula> <tex-math>$G_{max }$ </tex-math></inline-formula>\u0000-core is employed to simultaneously realize noise and power matching as well as provide high gain. A segmented design methodology for LNAs in terahertz band is employed to trade-off gain and noise. Incorporating the \u0000<inline-formula> <tex-math>$G_{max }$ </tex-math></inline-formula>\u0000-core with design methodology, a 220 GHz LNA is designed with balanced noise and gain performance. Fabricated using 40nm bulk CMOS process, measurement results reveal a minimum noise figure of 9.7 dB, a maximum gain of 24.8 dB between 214-225 GHz, and a saturated output power of −0.58 dBm at 220 GHz, while consuming only 36.9 mW. The LNA occupies a compact total area of 0.2 mm2, with a core area of 0.047 mm2. To the best of the authors’ knowledge, this represents the lowest noise figure achieved by LNA above 200 GHz using bulk CMOS technology.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 1","pages":"113-117"},"PeriodicalIF":4.0,"publicationDate":"2024-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142880417","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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