Pub Date : 2024-10-29DOI: 10.1109/TCSII.2024.3477193
{"title":"IEEE Circuits and Systems Society Information","authors":"","doi":"10.1109/TCSII.2024.3477193","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3477193","url":null,"abstract":"","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"71 11","pages":"C3-C3"},"PeriodicalIF":4.0,"publicationDate":"2024-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10738135","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142540415","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-29DOI: 10.1109/TCSII.2024.3477191
{"title":"IEEE Transactions on Circuits and Systems--II: Express Briefs Publication Information","authors":"","doi":"10.1109/TCSII.2024.3477191","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3477191","url":null,"abstract":"","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"71 11","pages":"C2-C2"},"PeriodicalIF":4.0,"publicationDate":"2024-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10738009","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142540418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-29DOI: 10.1109/TCSII.2024.3467908
Antonio Liscidini
{"title":"Guest Editorial Special Issue on the 2024 ISICAS: A CAS Journal Track Symposium","authors":"Antonio Liscidini","doi":"10.1109/TCSII.2024.3467908","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3467908","url":null,"abstract":"","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"71 11","pages":"4607-4607"},"PeriodicalIF":4.0,"publicationDate":"2024-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10738013","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142540378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-30DOI: 10.1109/TCSII.2024.3470111
Jae-Yun Park;Jae-Won Nam
A qubit-control waveform generator utilizing a 4-channel time-interleaved $Delta Sigma $ DAC is presented. A digital-to-analog converter (DAC) at 4.3 GS/s with an oversampling rate of 8 is fabricated in 65 nm CMOS technology. To enhance the linearity of the DAC, harmonic cancellation is proposed. Time-interleaving is applied in a $Delta Sigma $ modulator to widen the bandwidth. A high operational speed is also achieved through an unrolling technique to the direct digital frequency synthesis (DDFS) digital core. To ensure robustness of the process-voltage-temperature (PVT) variations, temperature-insensitive bias is proposed, with implementation mainly based on digital circuits. The proposed $Delta Sigma $ DAC consumes 256.04 mW of power, and the core area is $0.11~mm^{2}$ . The signal-to-noise distortion ratio (SNDR) and the spurious free dynamic range (SFDR) after enabling harmonic cancellation are respectively 30.62 dB and 47.03 dB at 100 K temperature.
{"title":"A 4.3 GS/s Time-Interleaved ΔΣ DAC With Temperature-Insensitive Bias and Harmonic Cancellation for Qubit Control","authors":"Jae-Yun Park;Jae-Won Nam","doi":"10.1109/TCSII.2024.3470111","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3470111","url":null,"abstract":"A qubit-control waveform generator utilizing a 4-channel time-interleaved \u0000<inline-formula> <tex-math>$Delta Sigma $ </tex-math></inline-formula>\u0000 DAC is presented. A digital-to-analog converter (DAC) at 4.3 GS/s with an oversampling rate of 8 is fabricated in 65 nm CMOS technology. To enhance the linearity of the DAC, harmonic cancellation is proposed. Time-interleaving is applied in a \u0000<inline-formula> <tex-math>$Delta Sigma $ </tex-math></inline-formula>\u0000 modulator to widen the bandwidth. A high operational speed is also achieved through an unrolling technique to the direct digital frequency synthesis (DDFS) digital core. To ensure robustness of the process-voltage-temperature (PVT) variations, temperature-insensitive bias is proposed, with implementation mainly based on digital circuits. The proposed \u0000<inline-formula> <tex-math>$Delta Sigma $ </tex-math></inline-formula>\u0000 DAC consumes 256.04 mW of power, and the core area is \u0000<inline-formula> <tex-math>$0.11~mm^{2}$ </tex-math></inline-formula>\u0000. The signal-to-noise distortion ratio (SNDR) and the spurious free dynamic range (SFDR) after enabling harmonic cancellation are respectively 30.62 dB and 47.03 dB at 100 K temperature.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"71 11","pages":"4663-4667"},"PeriodicalIF":4.0,"publicationDate":"2024-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142540381","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-26DOI: 10.1109/TCSII.2024.3462213
{"title":"TechRxiv: Share Your Preprint Research with the World!","authors":"","doi":"10.1109/TCSII.2024.3462213","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3462213","url":null,"abstract":"","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"71 10","pages":"4606-4606"},"PeriodicalIF":4.0,"publicationDate":"2024-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10695789","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142328417","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-26DOI: 10.1109/TCSII.2024.3462215
{"title":"IEEE Circuits and Systems Society Information","authors":"","doi":"10.1109/TCSII.2024.3462215","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3462215","url":null,"abstract":"","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"71 10","pages":"C3-C3"},"PeriodicalIF":4.0,"publicationDate":"2024-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10695787","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142328374","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-26DOI: 10.1109/TCSII.2024.3462211
{"title":"IEEE Transactions on Circuits and Systems--II: Express Briefs Publication Information","authors":"","doi":"10.1109/TCSII.2024.3462211","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3462211","url":null,"abstract":"","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"71 10","pages":"C2-C2"},"PeriodicalIF":4.0,"publicationDate":"2024-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10695795","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142324351","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This brief introduces a multi-level phase-change memory (PCM) readout circuit that realizes a true M-metric readout scheme that inherently has a wide dynamic input range. In order to overcome the limited readout speed of a basic M-metric scheme that draws a small current through a PCM cell over a large bit-line capacitance and senses the voltage, we propose an opamp-less M-metric readout circuit that drives the bit-line in a successive approximation manner with a comparator-based push-pull driver (CPPD). The bit-line driving speed of the proposed readout circuit is comparable with that of a conventional voltage driver, but the power consumption is greatly reduced owing to the absence of a power hungry opamp. The prototype design achieves a full 6-bit linearity and 245-uW power consumption at a 270-ns readout speed.
{"title":"An M-Metric Readout Circuit for MLC Phase-Change Memory With a Comparator-Based Push-Pull Bit-Line Driver","authors":"Ji-Wook Kwon;Dong-Hwan Jin;Min-Jae Seo;Seung-Tak Ryu","doi":"10.1109/TCSII.2024.3465888","DOIUrl":"https://doi.org/10.1109/TCSII.2024.3465888","url":null,"abstract":"This brief introduces a multi-level phase-change memory (PCM) readout circuit that realizes a true M-metric readout scheme that inherently has a wide dynamic input range. In order to overcome the limited readout speed of a basic M-metric scheme that draws a small current through a PCM cell over a large bit-line capacitance and senses the voltage, we propose an opamp-less M-metric readout circuit that drives the bit-line in a successive approximation manner with a comparator-based push-pull driver (CPPD). The bit-line driving speed of the proposed readout circuit is comparable with that of a conventional voltage driver, but the power consumption is greatly reduced owing to the absence of a power hungry opamp. The prototype design achieves a full 6-bit linearity and 245-uW power consumption at a 270-ns readout speed.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"71 11","pages":"4658-4662"},"PeriodicalIF":4.0,"publicationDate":"2024-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142540461","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-18DOI: 10.1109/tcsii.2024.3463200
Wenyue Zhang, Pingcheng Dong, Lei Chen, Zhengyu Ma, Fengwei An
{"title":"Min-Pooling Cost Aggregation for Semi-Global Matching of Stereo Vision Processor","authors":"Wenyue Zhang, Pingcheng Dong, Lei Chen, Zhengyu Ma, Fengwei An","doi":"10.1109/tcsii.2024.3463200","DOIUrl":"https://doi.org/10.1109/tcsii.2024.3463200","url":null,"abstract":"","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"20 1","pages":""},"PeriodicalIF":4.4,"publicationDate":"2024-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142268059","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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