Pub Date : 2025-02-27DOI: 10.1109/TCSII.2025.3541469
{"title":"IEEE Transactions on Circuits and Systems--II: Express Briefs Publication Information","authors":"","doi":"10.1109/TCSII.2025.3541469","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3541469","url":null,"abstract":"","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 3","pages":"C2-C2"},"PeriodicalIF":4.0,"publicationDate":"2025-02-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10906742","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143512887","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-02-27DOI: 10.1109/TCSII.2025.3541471
{"title":"IEEE Circuits and Systems Society Information","authors":"","doi":"10.1109/TCSII.2025.3541471","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3541471","url":null,"abstract":"","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 3","pages":"C3-C3"},"PeriodicalIF":4.0,"publicationDate":"2025-02-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10906691","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143512890","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-31DOI: 10.1109/TCSII.2025.3537617
Hadi Hayati;Saeed Ghaneei Aarani;Mousa Karimi;Razieh Eskandari;Mohamad Sawan;Gabriel Gagnon-Turcotte;Benoit Gosselin
This brief presents an impulse radio ultra-wideband (IR-UWB) transmitter (TX) designed for miniature multi-channel neural recording platforms in freely moving laboratory animals. We introduce a 5-bit data-to-time modulation technique utilizing a 5-cell capacitive array. This approach minimizes the data rate’s dependency on pulse repetition frequency, while significantly reducing power dissipation and simplifying the TX’s architecture. Measurement results with the TX fabricated in TSMC 65-nm standard CMOS technology show that the proposed circuit provides a linear time change in the pulsewidth with a time step of 84 ps in average for every least significant bit in the input. Furthermore, the entire circuit consumes only $422~{mu }$ W from a 0.65-V supply. The proposed TX achieves a significantly low energy consumption of 1.05 pJ/bit at 400 Mbps in a 0.5-m transmission range. The fabricated circuit occupies 0.255 mm2 of die area including pads.
{"title":"A 400-Mbps 1.05 pJ/Bit IR-UWB Transmitter for High-Density Neural Recording Systems","authors":"Hadi Hayati;Saeed Ghaneei Aarani;Mousa Karimi;Razieh Eskandari;Mohamad Sawan;Gabriel Gagnon-Turcotte;Benoit Gosselin","doi":"10.1109/TCSII.2025.3537617","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3537617","url":null,"abstract":"This brief presents an impulse radio ultra-wideband (IR-UWB) transmitter (TX) designed for miniature multi-channel neural recording platforms in freely moving laboratory animals. We introduce a 5-bit data-to-time modulation technique utilizing a 5-cell capacitive array. This approach minimizes the data rate’s dependency on pulse repetition frequency, while significantly reducing power dissipation and simplifying the TX’s architecture. Measurement results with the TX fabricated in TSMC 65-nm standard CMOS technology show that the proposed circuit provides a linear time change in the pulsewidth with a time step of 84 ps in average for every least significant bit in the input. Furthermore, the entire circuit consumes only <inline-formula> <tex-math>$422~{mu }$ </tex-math></inline-formula>W from a 0.65-V supply. The proposed TX achieves a significantly low energy consumption of 1.05 pJ/bit at 400 Mbps in a 0.5-m transmission range. The fabricated circuit occupies 0.255 mm2 of die area including pads.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 3","pages":"484-488"},"PeriodicalIF":4.0,"publicationDate":"2025-01-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143512897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-30DOI: 10.1109/TCSII.2025.3529370
{"title":"IEEE Transactions on Circuits and Systems--II: Express Briefs Publication Information","authors":"","doi":"10.1109/TCSII.2025.3529370","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3529370","url":null,"abstract":"","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 2","pages":"C2-C2"},"PeriodicalIF":4.0,"publicationDate":"2025-01-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10858350","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143107085","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-30DOI: 10.1109/TCSII.2025.3529372
{"title":"IEEE Circuits and Systems Society Information","authors":"","doi":"10.1109/TCSII.2025.3529372","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3529372","url":null,"abstract":"","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 2","pages":"C3-C3"},"PeriodicalIF":4.0,"publicationDate":"2025-01-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10858347","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143107012","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-28DOI: 10.1109/TCSII.2025.3535574
Mingliang Ding;Zhenhao Li;Wenhai Qi;Ju H. Park
The security control is studied for discrete nonhomogeneous semi-Markov switching power systems under network attacks. In view of time-varying transition probability, a nonhomogeneous semi-Markov chain is introduced to accurately model transient faults of power lines and dynamic switching of circuit breakers. Due to the random nature of denial-of-service (DoS) attacks, Bernoulli process is adopted to characterize the attacks behavior. Based on the semi-Markov kernel and Lyapunov function depending on the current system mode and dwell time, sufficient conditions for the existence of the controller are derived to ensure the mean-square stability of the closed-loop system. Finally, the effectiveness and practicability of the proposed control strategy are verified by a numerical case.
{"title":"Security Control for Networked Nonhomogeneous Stochastic Switching Power Systems With DoS Attacks","authors":"Mingliang Ding;Zhenhao Li;Wenhai Qi;Ju H. Park","doi":"10.1109/TCSII.2025.3535574","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3535574","url":null,"abstract":"The security control is studied for discrete nonhomogeneous semi-Markov switching power systems under network attacks. In view of time-varying transition probability, a nonhomogeneous semi-Markov chain is introduced to accurately model transient faults of power lines and dynamic switching of circuit breakers. Due to the random nature of denial-of-service (DoS) attacks, Bernoulli process is adopted to characterize the attacks behavior. Based on the semi-Markov kernel and Lyapunov function depending on the current system mode and dwell time, sufficient conditions for the existence of the controller are derived to ensure the mean-square stability of the closed-loop system. Finally, the effectiveness and practicability of the proposed control strategy are verified by a numerical case.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 3","pages":"519-523"},"PeriodicalIF":4.0,"publicationDate":"2025-01-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143512891","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-24DOI: 10.1109/TCSII.2025.3532628
Dong-Seob Shin;Young-Chan Jang
A clock and data recovery (CDR) with a voltage-controlled oscillator (VCO) calibration circuit is proposed for supporting transmission speeds from 1.62 Gbps to 10 Gbps. It has a dual-loop structure for frequency and phase locking while using a VCO based on a ring oscillator to support a wide operating range. The VCO calibration circuitry ensures that the VCO’s gain, kVCO, is set within a consistent range over a wide data rate by adaptively setting the operating frequency range of the VCO based on the frequency of the incoming training pattern. The proposed CDR is implemented by using a 40-nm CMOS process with a voltage supply of 1.2 V. It occupies the area of 0.08mm2 while having power efficiency of 2.5 pJ/bit. The proposed CDR improved the peak-to-peak time jitter of the recovered clock from 51.1ps to 31.25ps at the data rate of 8.1 Gbps by using the VCO calibration circuit. The proposed VCO calibration for the CDR also reduced the distribution of the peak-to-peak time jitter of the recovered clocks between the evaluated chips by 44%.
{"title":"A 1.62 – 10-Gb/s CDR Using Wide-Range VCO With Linearized KVCO","authors":"Dong-Seob Shin;Young-Chan Jang","doi":"10.1109/TCSII.2025.3532628","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3532628","url":null,"abstract":"A clock and data recovery (CDR) with a voltage-controlled oscillator (VCO) calibration circuit is proposed for supporting transmission speeds from 1.62 Gbps to 10 Gbps. It has a dual-loop structure for frequency and phase locking while using a VCO based on a ring oscillator to support a wide operating range. The VCO calibration circuitry ensures that the VCO’s gain, kVCO, is set within a consistent range over a wide data rate by adaptively setting the operating frequency range of the VCO based on the frequency of the incoming training pattern. The proposed CDR is implemented by using a 40-nm CMOS process with a voltage supply of 1.2 V. It occupies the area of 0.08mm2 while having power efficiency of 2.5 pJ/bit. The proposed CDR improved the peak-to-peak time jitter of the recovered clock from 51.1ps to 31.25ps at the data rate of 8.1 Gbps by using the VCO calibration circuit. The proposed VCO calibration for the CDR also reduced the distribution of the peak-to-peak time jitter of the recovered clocks between the evaluated chips by 44%.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 3","pages":"474-478"},"PeriodicalIF":4.0,"publicationDate":"2025-01-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143512984","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-22DOI: 10.1109/TCSII.2025.3532665
Eslam Elmitwalli;Zeljko Ignjatovic;Selçuk Köse
Ising machines are efficient hardware solvers for combinatorial optimization problems (COPs). In CMOS-based Ising machines, the annealing process is crucial for efficiently navigating complex energy landscapes in mapped COPs such as Max-Cut and low-density parity-check (LDPC) decoding. QuBRIM, a CMOS-based Ising machine, has recently been utilized to solve LDPC decoding problems using multi-body interactions. A constraint-aware annealing schedule is proposed that increases the efficiency of solving the mapped COP. The proposed annealing method uses knowledge of the LDPC decoding problem to guide the annealing process. The annealing schedule is demonstrated through high-level simulations. The proposed methodology demonstrates a normalized energy efficiency (NEE) of 0.68 pJ/bit/iteration, which is a 1.8x improvement over random bit-flip annealing, and an 80% increase in throughput.
{"title":"Constraint-Aware Annealing for CMOS-Based Ising Machine LDPC Decoder","authors":"Eslam Elmitwalli;Zeljko Ignjatovic;Selçuk Köse","doi":"10.1109/TCSII.2025.3532665","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3532665","url":null,"abstract":"Ising machines are efficient hardware solvers for combinatorial optimization problems (COPs). In CMOS-based Ising machines, the annealing process is crucial for efficiently navigating complex energy landscapes in mapped COPs such as Max-Cut and low-density parity-check (LDPC) decoding. QuBRIM, a CMOS-based Ising machine, has recently been utilized to solve LDPC decoding problems using multi-body interactions. A constraint-aware annealing schedule is proposed that increases the efficiency of solving the mapped COP. The proposed annealing method uses knowledge of the LDPC decoding problem to guide the annealing process. The annealing schedule is demonstrated through high-level simulations. The proposed methodology demonstrates a normalized energy efficiency (NEE) of 0.68 pJ/bit/iteration, which is a 1.8x improvement over random bit-flip annealing, and an 80% increase in throughput.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 3","pages":"479-483"},"PeriodicalIF":4.0,"publicationDate":"2025-01-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143512925","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-20DOI: 10.1109/TCSII.2025.3531710
Dan Shi;Ka-Meng Lei;Rui P. Martins;Pui-In Mak
This brief presents a fully integrated sub-0.5 V digital frequency-locked loop (DFLL) incorporating a clock-boosting RC network to secure frequency accuracy under ultra-low voltage (ULV) operation. It embodies 3 key features: 1) a clock-boosting RC network with a time constant $tau $ = RC to set the nominal frequency, 2) a dynamic tail-boosted comparator with offset background calibration to facilitate operation in ULV regime, and 3) a hybrid digital-controlled oscillator (DCO) with resolution enhancement to uphold the frequency stability. Fabricated in 65-nm CMOS, the DFLL features a compact footprint of 0.0136 mm2 and consumes $5.7~mu $ W under 0.35 V at room temperature. It achieves a line sensitivity of 1.06%/V across 0.35 to 0.5 V, and a frequency inaccuracy of 176 ppm/°C between −30 and 120 ° C. Benefitting from the offset calibration technique to reduce the inband noise, the DFLL demonstrates outstanding jitter $Fo{mathrm { M}}_{mathrm { Jitter}}$ of −224.5 dB and Allan deviation floor of <5 ppm, showcasing exceptional frequency stability.
{"title":"A 0.35–0.5-V 0.0136-mm² 12 -MHz Digital Frequency-Locked Loop With 1.06%/V Line Sensitivity in 65-nm CMOS","authors":"Dan Shi;Ka-Meng Lei;Rui P. Martins;Pui-In Mak","doi":"10.1109/TCSII.2025.3531710","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3531710","url":null,"abstract":"This brief presents a fully integrated sub-0.5 V digital frequency-locked loop (DFLL) incorporating a clock-boosting RC network to secure frequency accuracy under ultra-low voltage (ULV) operation. It embodies 3 key features: 1) a clock-boosting RC network with a time constant <inline-formula> <tex-math>$tau $ </tex-math></inline-formula> = RC to set the nominal frequency, 2) a dynamic tail-boosted comparator with offset background calibration to facilitate operation in ULV regime, and 3) a hybrid digital-controlled oscillator (DCO) with resolution enhancement to uphold the frequency stability. Fabricated in 65-nm CMOS, the DFLL features a compact footprint of 0.0136 mm2 and consumes <inline-formula> <tex-math>$5.7~mu $ </tex-math></inline-formula> W under 0.35 V at room temperature. It achieves a line sensitivity of 1.06%/V across 0.35 to 0.5 V, and a frequency inaccuracy of 176 ppm/°C between −30 and 120 ° C. Benefitting from the offset calibration technique to reduce the inband noise, the DFLL demonstrates outstanding jitter <inline-formula> <tex-math>$Fo{mathrm { M}}_{mathrm { Jitter}}$ </tex-math></inline-formula> of −224.5 dB and Allan deviation floor of <5 ppm, showcasing exceptional frequency stability.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 3","pages":"459-463"},"PeriodicalIF":4.0,"publicationDate":"2025-01-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143512900","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this brief, an inductor-less low-noise amplifier (LNA) that utilizes a noise-canceling technique along with dual-resistor feedback is proposed. The conventional single-resistor feedback structure exhibits a performance constraint that limits the relationship between power gain and input matching. In contrast, the dual-resistor feedback structure proposed in this brief overcomes this limitation, enabling both high gain and low noise while maintaining good input matching. The dual-resistor feedback configuration includes a local feedback resistor which enhances the gain. Additionally, the global feedback resistor directly connect the inputs and outputs of the circuit, thereby breaking the constraints between the properties through feedback. The proposed LNA fabricated in 65-nm CMOS technology exhibiting a minimal NF of 2.08 dB within a 3-dB bandwidth that spans from 0.25 to 2.83 GHz, along with a peak power gain of 16.53 dB. The circuit operates with a power consumption of 10.6 mW under a supply voltage of 1.1 V, while occupying a core area of only 0.012 mm2.
{"title":"A 0.2-3 GHz Inductor-Less LNA Using Noise-Canceling and Dual-Resistor Feedback Technique","authors":"Junfan Yan;Wenjie Feng;Pei Qin;Haoshen Zhu;Yunfei Cao;Wenquan Che;Quan Xue","doi":"10.1109/TCSII.2025.3531994","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3531994","url":null,"abstract":"In this brief, an inductor-less low-noise amplifier (LNA) that utilizes a noise-canceling technique along with dual-resistor feedback is proposed. The conventional single-resistor feedback structure exhibits a performance constraint that limits the relationship between power gain and input matching. In contrast, the dual-resistor feedback structure proposed in this brief overcomes this limitation, enabling both high gain and low noise while maintaining good input matching. The dual-resistor feedback configuration includes a local feedback resistor which enhances the gain. Additionally, the global feedback resistor directly connect the inputs and outputs of the circuit, thereby breaking the constraints between the properties through feedback. The proposed LNA fabricated in 65-nm CMOS technology exhibiting a minimal NF of 2.08 dB within a 3-dB bandwidth that spans from 0.25 to 2.83 GHz, along with a peak power gain of 16.53 dB. The circuit operates with a power consumption of 10.6 mW under a supply voltage of 1.1 V, while occupying a core area of only 0.012 mm2.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 3","pages":"469-473"},"PeriodicalIF":4.0,"publicationDate":"2025-01-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143512983","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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