Pub Date : 2026-01-06DOI: 10.1109/TCSII.2025.3641493
{"title":"IEEE Circuits and Systems Society Information","authors":"","doi":"10.1109/TCSII.2025.3641493","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3641493","url":null,"abstract":"","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 1","pages":"C3-C3"},"PeriodicalIF":4.9,"publicationDate":"2026-01-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11330180","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145904304","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-01-06DOI: 10.1109/TCSII.2025.3641491
{"title":"IEEE Transactions on Circuits and Systems--II: Express Briefs Publication Information","authors":"","doi":"10.1109/TCSII.2025.3641491","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3641491","url":null,"abstract":"","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 1","pages":"C2-C2"},"PeriodicalIF":4.9,"publicationDate":"2026-01-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11330183","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145904325","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-01-06DOI: 10.1109/TCSII.2025.3633439
Edoardo Bonizzoni
{"title":"Incoming Editorial","authors":"Edoardo Bonizzoni","doi":"10.1109/TCSII.2025.3633439","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3633439","url":null,"abstract":"","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 1","pages":"1-2"},"PeriodicalIF":4.9,"publicationDate":"2026-01-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11330184","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145904295","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-04DOI: 10.1109/TCSII.2025.3640485
{"title":"2025 Index IEEE Transactions on Circuits and Systems--II","authors":"","doi":"10.1109/TCSII.2025.3640485","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3640485","url":null,"abstract":"","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 12","pages":"1-102"},"PeriodicalIF":4.9,"publicationDate":"2025-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11278479","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145674664","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-01DOI: 10.1109/TCSII.2025.3638907
Nengxu Zhu;Yiting Zhang;Zenglong Zhao;Fanyi Meng
This brief presents a compact DC-to-6 GHz single-pole double-throw (SPDT) switch utilizing embedded RLC resonator technology. Building upon the traditional series-shunt RCstructure, an inductor is incorporated between the series and shunt transistors, working in conjunction with the port-matching inductors to achieve broadband low-loss characteristics in the through mode. In the isolation mode, the structure forms an RLC resonator to enhance isolation. To improve linearity, quadruple-stacked transistors are employed for both the series and shunt-switching transistors. Fabricated using the SMIC $0.13~mu $ m CMOS SOI process, the measurement results demonstrate that the chip achieves an isolation of >50 dB across the DC-to-6 GHz range, with an insertion loss of only 0.4–1.2 dB and an input power at 1 dB compression point (IP1dB) of 20 dBm at 5 GHz. The core area of the chip is only 0.06 mm2.
{"title":"Design of a Compact Wideband SPDT Switch With High Isolation for Sub-6 GHz Applications","authors":"Nengxu Zhu;Yiting Zhang;Zenglong Zhao;Fanyi Meng","doi":"10.1109/TCSII.2025.3638907","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3638907","url":null,"abstract":"This brief presents a compact DC-to-6 GHz single-pole double-throw (SPDT) switch utilizing embedded <italic>RLC</i> resonator technology. Building upon the traditional series-shunt <italic>RC</i>structure, an inductor is incorporated between the series and shunt transistors, working in conjunction with the port-matching inductors to achieve broadband low-loss characteristics in the through mode. In the isolation mode, the structure forms an <italic>RLC</i> resonator to enhance isolation. To improve linearity, quadruple-stacked transistors are employed for both the series and shunt-switching transistors. Fabricated using the SMIC <inline-formula> <tex-math>$0.13~mu $ </tex-math></inline-formula>m CMOS SOI process, the measurement results demonstrate that the chip achieves an isolation of >50 dB across the DC-to-6 GHz range, with an insertion loss of only 0.4–1.2 dB and an input power at 1 dB compression point (IP<sub>1dB</sub>) of 20 dBm at 5 GHz. The core area of the chip is only 0.06 mm<sup>2</sup>.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 1","pages":"43-47"},"PeriodicalIF":4.9,"publicationDate":"2025-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145904315","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-26DOI: 10.1109/TCSII.2025.3637298
Gaoyuan Zhao;Xiangyu Meng;Pengfei Bai;Baoyong Chi
This brief presents a 5-bit CMOS attenuator employing an NMOS on-resistance self-locking technique to address temperature drift and process variations in millimeter-wave phased arrays. Unlike conventional polysilicon resistor networks, the proposed design features an all-NMOS attenuation network operating in the deep linear region, leveraging transistor parasitic capacitance for intrinsic phase compensation. A closed-loop feedback mechanism dynamically stabilizes on-resistance by real-time gate bias adjustment, eliminating external tuning while suppressing PVT variations across DC–30 GHz. Measurement results demonstrate 0.46 dB RMS amplitude error and 1.77° RMS phase error, with cross-chip comparisons revealing process variation tolerance: inter-chip discrepancies remain below 0.06 dB (gain) and 1.36° (phase). The self-locking loop achieves fully automatic impedance stabilization with $868~mu $ W power consumption and 0.0148 mm2 core area in 65 nm CMOS.
{"title":"A DC-to-30 GHz NMOS Attenuator With Constant MOSFET On-Resistance","authors":"Gaoyuan Zhao;Xiangyu Meng;Pengfei Bai;Baoyong Chi","doi":"10.1109/TCSII.2025.3637298","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3637298","url":null,"abstract":"This brief presents a 5-bit CMOS attenuator employing an NMOS on-resistance self-locking technique to address temperature drift and process variations in millimeter-wave phased arrays. Unlike conventional polysilicon resistor networks, the proposed design features an all-NMOS attenuation network operating in the deep linear region, leveraging transistor parasitic capacitance for intrinsic phase compensation. A closed-loop feedback mechanism dynamically stabilizes on-resistance by real-time gate bias adjustment, eliminating external tuning while suppressing PVT variations across DC–30 GHz. Measurement results demonstrate 0.46 dB RMS amplitude error and 1.77° RMS phase error, with cross-chip comparisons revealing process variation tolerance: inter-chip discrepancies remain below 0.06 dB (gain) and 1.36° (phase). The self-locking loop achieves fully automatic impedance stabilization with <inline-formula> <tex-math>$868~mu $ </tex-math></inline-formula>W power consumption and 0.0148 mm<sup>2</sup> core area in 65 nm CMOS.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 1","pages":"33-37"},"PeriodicalIF":4.9,"publicationDate":"2025-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145904309","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This brief presents a 25-Mbps 4-amplitude-shift-keying (4-ASK) receiver front-end (RFE) for biomedical data telemetry via a series-resonant capacitive link. The RFE incorporates low-power clock and data recovery (CDR) circuitry for synchronization in which a novel highly linear transconductance ($G_{mathbf {m}}$ ) cell is employed in the phase detector (PD) to mitigate any possible error decisions while comparing the phase difference between the input and feedback signals. The proposed RFE is fabricated in 65 nm 1P8M standard CMOS, the core circuit occupies 0.11 mm${}^{mathbf {2}}$ , and consumes 2.9 mA from 1 V. While conducting $ex ~vivo$ measurements using beef tissue and a series-resonant capacitive link, the proposed RFE is capable of processing 4-ASK data patterns up to 25 Mbps with bit error rate (BER) less than $10^{mathbf {-3}}$ and total jitter of ~42 ns.
{"title":"A 25-Mb/s 4-ASK Receiver Front-End in 65-nm CMOS for Biomedical Data Telemetry via a Capacitive Link","authors":"Hossein Yaghobi;Mohammad Mobaraki;Pedram Mohseni;Hossein Miri Lavasani","doi":"10.1109/TCSII.2025.3637697","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3637697","url":null,"abstract":"This brief presents a 25-Mbps 4-amplitude-shift-keying (4-ASK) receiver front-end (RFE) for biomedical data telemetry via a series-resonant capacitive link. The RFE incorporates low-power clock and data recovery (CDR) circuitry for synchronization in which a novel highly linear transconductance (<inline-formula> <tex-math>$G_{mathbf {m}}$ </tex-math></inline-formula>) cell is employed in the phase detector (PD) to mitigate any possible error decisions while comparing the phase difference between the input and feedback signals. The proposed RFE is fabricated in 65 nm 1P8M standard CMOS, the core circuit occupies 0.11 mm<inline-formula> <tex-math>${}^{mathbf {2}}$ </tex-math></inline-formula>, and consumes 2.9 mA from 1 V. While conducting <inline-formula> <tex-math>$ex ~vivo$ </tex-math></inline-formula> measurements using beef tissue and a series-resonant capacitive link, the proposed RFE is capable of processing 4-ASK data patterns up to 25 Mbps with bit error rate (BER) less than <inline-formula> <tex-math>$10^{mathbf {-3}}$ </tex-math></inline-formula> and total jitter of ~42 ns.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 1","pages":"38-42"},"PeriodicalIF":4.9,"publicationDate":"2025-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145904345","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-25DOI: 10.1109/TCSII.2025.3632713
{"title":"IEEE Circuits and Systems Society Information","authors":"","doi":"10.1109/TCSII.2025.3632713","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3632713","url":null,"abstract":"","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 12","pages":"C3-C3"},"PeriodicalIF":4.9,"publicationDate":"2025-11-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11268902","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145595127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-21DOI: 10.1109/TCSII.2025.3635634
Bowen Ding;Ying Song;Lihua Dai;Shuiyang Lin
This article presents a 7-bit high-resolution hybrid vector-modulated (VM) variable gain phase shifter (VGPS) with 1-bit Capacitive Digital-to-Analog Converter (CDAC) in CMOS. Cross-coupled differential common-source pairs are used to form 11-step phase-invariant (PI) variable gain amplifiers (VGAs), ensuring consistent phase and suitable output impedance across varying gain and phase settings. To further improve phase resolution, a 1-bit CDAC is inserted between the coupler-based in-phase and quadrature generator (IQG) and the PI VGA. This integration mitigates typical CDAC drawbacks, such as variations in input/output return loss and sensitivity to VGA load impedance, without introducing phase or gain imbalances in the IQ paths. Measurements show that the proposed VGPS provides a 6 dB gain tuning range and monotonic phase response. It achieves 7-bit phase resolution over 70-85 GHz, with a root-mean-square (RMS) phase error less than 3° and RMS gain error of 0.5 dB. The circuit consumes 30 mW from a 0.9 V supply and occupies a compact core area of $425~mu $ m $times 320~mu $ m.
本文介绍了一种7位高分辨率混合矢量调制（VM）可变增益移相器（VGPS），该移相器具有1位电容式数模转换器（CDAC）。交叉耦合差分共源对用于形成11步相位不变（PI）变增益放大器（VGAs），确保在不同增益和相位设置下相位一致和合适的输出阻抗。为了进一步提高相位分辨率，在基于耦合器的同相和正交发生器（IQG）和PI VGA之间插入1位CDAC。这种集成减轻了典型的CDAC缺点，例如输入/输出返回损耗的变化和对VGA负载阻抗的灵敏度，而不会在IQ路径中引入相位或增益不平衡。测量结果表明，所提出的VGPS具有6 dB增益调谐范围和单调相位响应。在70-85 GHz范围内实现7位相位分辨率，均方根（RMS）相位误差小于3°，RMS增益误差为0.5 dB。该电路从0.9 V的电源消耗30 mW，并占用紧凑的核心面积$425~mu $ m $ × 320~mu $ m $ m。
{"title":"A 7-bit 76–81-GHz Hybrid Vector-Modulated Variable Gain Phase Shifter Combining Phase-Invariant VGA and 1-bit CDAC","authors":"Bowen Ding;Ying Song;Lihua Dai;Shuiyang Lin","doi":"10.1109/TCSII.2025.3635634","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3635634","url":null,"abstract":"This article presents a 7-bit high-resolution hybrid vector-modulated (VM) variable gain phase shifter (VGPS) with 1-bit Capacitive Digital-to-Analog Converter (CDAC) in CMOS. Cross-coupled differential common-source pairs are used to form 11-step phase-invariant (PI) variable gain amplifiers (VGAs), ensuring consistent phase and suitable output impedance across varying gain and phase settings. To further improve phase resolution, a 1-bit CDAC is inserted between the coupler-based in-phase and quadrature generator (IQG) and the PI VGA. This integration mitigates typical CDAC drawbacks, such as variations in input/output return loss and sensitivity to VGA load impedance, without introducing phase or gain imbalances in the IQ paths. Measurements show that the proposed VGPS provides a 6 dB gain tuning range and monotonic phase response. It achieves 7-bit phase resolution over 70-85 GHz, with a root-mean-square (RMS) phase error less than 3° and RMS gain error of 0.5 dB. The circuit consumes 30 mW from a 0.9 V supply and occupies a compact core area of <inline-formula> <tex-math>$425~mu $ </tex-math></inline-formula>m <inline-formula> <tex-math>$times 320~mu $ </tex-math></inline-formula>m.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 1","pages":"28-32"},"PeriodicalIF":4.9,"publicationDate":"2025-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145904333","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This brief presents a high-linearity third-order 3-bit continuous-time delta-sigma modulator (CTDSM) with 109 dB spurious-free dynamic range (SFDR) for audio applications. The proposed modulator employs a cascade of integrators with feedforward structure using active RC integrators, a 3-bit flash quantizer, and resistor digital-to-analog converter (DAC) feedback. To address both DAC non-linearity and the tonal issues caused by conventional data weighted averaging (DWA), a new bi-directional advancing DWA (Bi-ADWA) with tone-suppressing and tone-transferring capabilities is introduced. Furthermore, the asymmetry in the rise/fall time of the DAC due to the additional paths introduced by Bi-ADWA is mitigated by optimizing the switch control circuitry and layout of the feedback DAC. Fabricated in a 180 nm CMOS technology, the modulator demonstrates a peak SNDR of 95.8 dB alongside a DR of 102.5 dB, consuming 0.58 mW at 1.8 V within an active area of 0.8 mm2.
{"title":"A 109-dB SFDR Continuous-Time Delta-Sigma Modulator for Audio Using Bi-Directional Advancing Data Weighted Averaging","authors":"Aoyun Sun;Lingling Wei;Hong Yang;Gang Liu;Zhang Zhang","doi":"10.1109/TCSII.2025.3635133","DOIUrl":"https://doi.org/10.1109/TCSII.2025.3635133","url":null,"abstract":"This brief presents a high-linearity third-order 3-bit continuous-time delta-sigma modulator (CTDSM) with 109 dB spurious-free dynamic range (SFDR) for audio applications. The proposed modulator employs a cascade of integrators with feedforward structure using active RC integrators, a 3-bit flash quantizer, and resistor digital-to-analog converter (DAC) feedback. To address both DAC non-linearity and the tonal issues caused by conventional data weighted averaging (DWA), a new bi-directional advancing DWA (Bi-ADWA) with tone-suppressing and tone-transferring capabilities is introduced. Furthermore, the asymmetry in the rise/fall time of the DAC due to the additional paths introduced by Bi-ADWA is mitigated by optimizing the switch control circuitry and layout of the feedback DAC. Fabricated in a 180 nm CMOS technology, the modulator demonstrates a peak SNDR of 95.8 dB alongside a <italic>DR</i> of 102.5 dB, consuming 0.58 mW at 1.8 V within an active area of 0.8 mm<sup>2</sup>.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"73 1","pages":"23-27"},"PeriodicalIF":4.9,"publicationDate":"2025-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145904328","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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