{"title":"A 5-GHz Quadrature Switched-Capacitor Power Amplifier With IQ-Cell-Sharing and Serial Transformer Combiner in 28-nm CMOS","authors":"Diyang Zheng;Yicheng Li;Hang Chen;Yun Yin;Hongtao Xu","doi":"10.1109/LMWT.2024.3405498","DOIUrl":null,"url":null,"abstract":"This letter presents a 5-GHz quadrature digital power amplifier (DPA) with serial transformer power combiner and in-phase and quadrature (IQ)-cell-sharing, which overcomes the 3-dB power loss in the conventional quadrature counterpart. A four-way differential serial-combining transformer (SCT) power combiner is adopted for output power close to the watt level. Implemented in 28-nm CMOS technology, the DPA is powered by 1.1-/2.2-V power supplies and only occupies \n<inline-formula> <tex-math>$0.98\\times 0.58$ </tex-math></inline-formula>\n mm2 core area. It achieves 28.6-dBm peak output power with power added efficiency (PAE) of 24.4% at 5 GHz. With 20-MHz 64-quadraticamplitude modulation (QAM) 802.11ac signal, the DPA achieves Pavg of 18.6 dBm and average PAE of 10.7% with −25.0 dB error vector magnitude (EVM) at 5 GHz with digital predistortion (DPD).","PeriodicalId":73297,"journal":{"name":"IEEE microwave and wireless technology letters","volume":"34 7","pages":"919-922"},"PeriodicalIF":3.4000,"publicationDate":"2024-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE microwave and wireless technology letters","FirstCategoryId":"1085","ListUrlMain":"https://ieeexplore.ieee.org/document/10550918/","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"0","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
This letter presents a 5-GHz quadrature digital power amplifier (DPA) with serial transformer power combiner and in-phase and quadrature (IQ)-cell-sharing, which overcomes the 3-dB power loss in the conventional quadrature counterpart. A four-way differential serial-combining transformer (SCT) power combiner is adopted for output power close to the watt level. Implemented in 28-nm CMOS technology, the DPA is powered by 1.1-/2.2-V power supplies and only occupies
$0.98\times 0.58$
mm2 core area. It achieves 28.6-dBm peak output power with power added efficiency (PAE) of 24.4% at 5 GHz. With 20-MHz 64-quadraticamplitude modulation (QAM) 802.11ac signal, the DPA achieves Pavg of 18.6 dBm and average PAE of 10.7% with −25.0 dB error vector magnitude (EVM) at 5 GHz with digital predistortion (DPD).
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