Subthreshold read operations in 3D PCM: 1S1R device modeling and memory array analysis

Abstract

3-D phase change memory (PCM) is one of the most promising next-generation nonvolatile memory, and the subthreshold sensing strategy can effectively improve its limited endurance. In this study, we propose a one-selector-one-resistor (1S1R) model with Monte Carlo (MC) function and provide array configurations for the worst case and the maximum bit line voltage (V_BL-max), respectively. Based on these, the read window margin (RWM) is evaluated with various array sizes, OTS threshold voltage variations (${\sigma }_{\mathrm{var}}$), and bias voltages (V_Bias). Our results reveal that the RWM increases as the V_BL approaches the V_BL-max. Larger arrays lead to an increased leakage current difference, while larger ${\sigma }_{\mathrm{var}}$ values result in decreased cell current difference and V_BL-max. The decrease in V_BL-max further deteriorates the RWM. Additionally, we analyze the optimal V_Bias for 2-deck arrays achieves a 7% reduction in leakage energy consumption and a 22.6% increase in RWM compared to the V/2 bias. The optimal V_Bias depends on OTS devices and array sizes.