Pub Date : 2025-03-13DOI: 10.1016/j.mee.2025.112343
Biaohong Huang , Yuxuan Jiang , Jingyan Liu , Yizhuo Li , Qianhe Jin , Qishuai Huang , Tula R. Paudel , Tom Wu , Zhidong Zhang , Weijin Hu
Ferroelectric materials are promising for nonvolatile resistive memories due to their unique switchable diode effect. To improve the resistive switching performance, the fundamental correlation between the diode effect and the polar ordering should be unraveled. Here by the A-site substitution with Sm, we report the resistive switching in ferroelectric SrRuO3/SmxBi1-xFeO3 (x = 0, 0.1, 0.2)/Pt thin-film capacitors. We find that the ground state of BiFeO3 changes from ferroelectric to antiferroelectric with increasing Sm substitution, which is accompanied by the fading of the resistive switching in Sm0.2Bi0.8FeO3, illustrating the decisive role of polarization in resistive switching. Moreover, similar dynamics between polarization and resistance states supports the close link between the ferroelectric domain growth and the resistive switching. Our SrRuO3/Sm0.1Bi0.9FeO3/Pt device achieved a high on/off ratio of 104 and fast switching speed of 6.25 ns, thanks to reduced leakage current from Sm doping while preserving ferroelectric properties. Our results thus provide a new approach to enhance the resistive memory performance of ferroelectric materials.
{"title":"Enhancing ferroelectric resistive switching via polar order engineering in Sm-doped BiFeO3 films","authors":"Biaohong Huang , Yuxuan Jiang , Jingyan Liu , Yizhuo Li , Qianhe Jin , Qishuai Huang , Tula R. Paudel , Tom Wu , Zhidong Zhang , Weijin Hu","doi":"10.1016/j.mee.2025.112343","DOIUrl":"10.1016/j.mee.2025.112343","url":null,"abstract":"<div><div>Ferroelectric materials are promising for nonvolatile resistive memories due to their unique switchable diode effect. To improve the resistive switching performance, the fundamental correlation between the diode effect and the polar ordering should be unraveled. Here by the A-site substitution with Sm, we report the resistive switching in ferroelectric SrRuO<sub>3</sub>/Sm<sub><em>x</em></sub>Bi<sub>1-<em>x</em></sub>FeO<sub>3</sub> (<em>x</em> = 0, 0.1, 0.2)/Pt thin-film capacitors. We find that the ground state of BiFeO<sub>3</sub> changes from ferroelectric to antiferroelectric with increasing Sm substitution, which is accompanied by the fading of the resistive switching in Sm<sub>0.2</sub>Bi<sub>0.8</sub>FeO<sub>3</sub>, illustrating the decisive role of polarization in resistive switching. Moreover, similar dynamics between polarization and resistance states supports the close link between the ferroelectric domain growth and the resistive switching. Our SrRuO<sub>3</sub>/Sm<sub>0.1</sub>Bi<sub>0.9</sub>FeO<sub>3</sub>/Pt device achieved a high on/off ratio of 10<sup>4</sup> and fast switching speed of 6.25 ns, thanks to reduced leakage current from Sm doping while preserving ferroelectric properties. Our results thus provide a new approach to enhance the resistive memory performance of ferroelectric materials.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"299 ","pages":"Article 112343"},"PeriodicalIF":2.6,"publicationDate":"2025-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143681859","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-10DOI: 10.1016/j.mee.2025.112334
P. Favia , G. Eneman , A. Veloso , A. Nalin Mehta , G.T. Martinez , O. Richard , A. Hikavyy , P.P. Gowda , F. Seidel , G. Pourtois , A. De Keersgieter , E. Grieten
Strain engineering is a common approach for enhancing the mobility of semiconductor materials and improving the performance of conventional and novel transistors. Understanding the strain distribution is important for optimizing device characteristics. Transmission electron microscopy (TEM) is a crucial technique for evaluating strain at the nanoscale. However, due to the ongoing reduction in electronic device dimensions, assessing strain via TEM has become increasingly challenging. Many different techniques have been developed in recent years with the aim of analysing complex structures. In this work, we investigate the capabilities of the recently developed Bessel beam electron diffraction (BBED) method to evaluate strain by TEM in fully processed fin-field effect transistor (FinFET) devices and in cutting edge nano-sheet complementary-FET (NS-CFET) technology.
TEM analysis of fully processed devices is challenging due to the presence of artefacts generated by different materials and multiple structures overlapping in projection in TEM images. We demonstrate the capability of the BBED technique to reveal strain in fully processed FinFET while exploring the dependence of strain on layout variations.
NS-CFETs are an attractive device architecture for beyond 1 nm logic technology nodes. Strain distribution in these devices is more complex than in FinFETs due to the presence of very thin layers and reduced channel dimensions. We compare the BBED method with the well-known techniques of nano-beam electron diffraction (NBED) and geometric phase analysis (GPA) for analysing strain in these structures. The BBED technique, despite a simple experimental setup, shows good accuracy and spatial resolution, being able to resolve interlayers thinner than 2 nm. Compared to NBED and GPA, the BBED technique offers better performance and is therefore a promising method to study strain in future transistor devices.
{"title":"Unveiling strain in future generation transistor technology by Bessel beam electron diffraction method","authors":"P. Favia , G. Eneman , A. Veloso , A. Nalin Mehta , G.T. Martinez , O. Richard , A. Hikavyy , P.P. Gowda , F. Seidel , G. Pourtois , A. De Keersgieter , E. Grieten","doi":"10.1016/j.mee.2025.112334","DOIUrl":"10.1016/j.mee.2025.112334","url":null,"abstract":"<div><div>Strain engineering is a common approach for enhancing the mobility of semiconductor materials and improving the performance of conventional and novel transistors. Understanding the strain distribution is important for optimizing device characteristics. Transmission electron microscopy (TEM) is a crucial technique for evaluating strain at the nanoscale. However, due to the ongoing reduction in electronic device dimensions, assessing strain via TEM has become increasingly challenging. Many different techniques have been developed in recent years with the aim of analysing complex structures. In this work, we investigate the capabilities of the recently developed Bessel beam electron diffraction (BBED) method to evaluate strain by TEM in fully processed fin-field effect transistor (FinFET) devices and in cutting edge nano-sheet complementary-FET (NS-CFET) technology.</div><div>TEM analysis of fully processed devices is challenging due to the presence of artefacts generated by different materials and multiple structures overlapping in projection in TEM images. We demonstrate the capability of the BBED technique to reveal strain in fully processed FinFET while exploring the dependence of strain on layout variations.</div><div>NS-CFETs are an attractive device architecture for beyond 1 nm logic technology nodes. Strain distribution in these devices is more complex than in FinFETs due to the presence of very thin layers and reduced channel dimensions. We compare the BBED method with the well-known techniques of nano-beam electron diffraction (NBED) and geometric phase analysis (GPA) for analysing strain in these structures. The BBED technique, despite a simple experimental setup, shows good accuracy and spatial resolution, being able to resolve interlayers thinner than 2 nm. Compared to NBED and GPA, the BBED technique offers better performance and is therefore a promising method to study strain in future transistor devices.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"299 ","pages":"Article 112334"},"PeriodicalIF":2.6,"publicationDate":"2025-03-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143637046","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-10DOI: 10.1016/j.mee.2025.112342
J. Ajayan , S. Sreejith
The power amplifiers (PAs) are indispensable for maintaining that both space and terrestrial transmitters fulfill the rigorous requirements for power consumption and, consequently, efficiency. Since solid-state PAs based on GaN HEMTs may offer the efficiency and power density performance to make them a feasible choice for space-borne active antennas, their availability is what propels integration for the satellite transmitters. Gain, output power (Pout), bandwidth (BW), drain efficiency (DE), chip area, peak-to-average-power ratio (PAPR) and power added efficiency (PAE) are the key metrics usually used for measuring the performance of PAs. This article deals with the exciting prospects and challenges in the design and manufacturing of GaN-HEMT based RF-PAs. Doherty PAs are most popular among various PA architectures and they have recorded a maximum gain of over 30 dB, PAPR of over 11.5, PAE of over 81 % and an operating frequency of over 29 GHz. Other GaN HEMT based PAs have been reported a maximum operating frequency of over 192 GHz (using 100 nm GaN HEMT), gain of over 35 dB, and a Pout of over 282 W. This article also highlights the various techniques for enhancing the broadband operation of GaN HEMT based PAs.
{"title":"AlGaN/GaN High electron Mobility Transistor (HEMT) based radio frequency power amplifiers for future wireless communication transmitters: Exciting prospects and challenges","authors":"J. Ajayan , S. Sreejith","doi":"10.1016/j.mee.2025.112342","DOIUrl":"10.1016/j.mee.2025.112342","url":null,"abstract":"<div><div>The power amplifiers (PAs) are indispensable for maintaining that both space and terrestrial transmitters fulfill the rigorous requirements for power consumption and, consequently, efficiency. Since solid-state PAs based on GaN HEMTs may offer the efficiency and power density performance to make them a feasible choice for space-borne active antennas, their availability is what propels integration for the satellite transmitters. Gain, output power (P<sub>out</sub>), bandwidth (BW), drain efficiency (DE), chip area, peak-to-average-power ratio (PAPR) and power added efficiency (PAE) are the key metrics usually used for measuring the performance of PAs. This article deals with the exciting prospects and challenges in the design and manufacturing of GaN-HEMT based RF-PAs. Doherty PAs are most popular among various PA architectures and they have recorded a maximum gain of over 30 dB, PAPR of over 11.5, PAE of over 81 % and an operating frequency of over 29 GHz. Other GaN HEMT based PAs have been reported a maximum operating frequency of over 192 GHz (using 100 nm GaN HEMT), gain of over 35 dB, and a P<sub>out</sub> of over 282 W. This article also highlights the various techniques for enhancing the broadband operation of GaN HEMT based PAs.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"299 ","pages":"Article 112342"},"PeriodicalIF":2.6,"publicationDate":"2025-03-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143593026","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-08DOI: 10.1016/j.mee.2025.112333
Rittik Ghosh, Alexandros Provias, Alexander Karl, Christoph Wilhelmer, Theresia Knobloch, Mohammad Rasool Davoudi, Seyed Mehdi Sattari-Esfahlan, Dominic Waldhör, Tibor Grasser
Threshold voltage hysteresis in two-dimensional transistor transfer characteristics poses a bottleneck in achieving stable 2D CMOS integrated circuits. Hysteresis is primarily attributed to traps at the channel/oxide interface as well as in the oxide. In this study, we present a physics-based self-consistent modeling framework to investigate the impact of border and interface traps on and apply it to monolayer (1-L) MoS2 field-effect transistors (FETs). The transient trapping and detrapping of charges during gate voltage sweeps across a wide range of frequencies and temperatures is analyzed using a two-state non-radiative multi-phonon (NMP) model. Our results reveal distinct dynamic responses for slow border and fast interface traps, with border traps exhibiting slower time constants due to larger relaxation energies and interface traps showing fast nuclear tunneling-dominated dynamics resulting from the smaller relaxation energies. These simulations highlights the critical role of the spatial and energetic distributions of the traps in determining , providing insights into the stability of 2D FETs and paving the way for improved device engineering.
{"title":"Theoretical insights into the impact of border and interface traps on hysteresis in monolayer MoS2 FETs","authors":"Rittik Ghosh, Alexandros Provias, Alexander Karl, Christoph Wilhelmer, Theresia Knobloch, Mohammad Rasool Davoudi, Seyed Mehdi Sattari-Esfahlan, Dominic Waldhör, Tibor Grasser","doi":"10.1016/j.mee.2025.112333","DOIUrl":"10.1016/j.mee.2025.112333","url":null,"abstract":"<div><div>Threshold voltage hysteresis <span><math><mfenced><mrow><mi>Δ</mi><msub><mi>V</mi><mi>h</mi></msub></mrow></mfenced></math></span> in two-dimensional transistor transfer characteristics poses a bottleneck in achieving stable 2D CMOS integrated circuits. Hysteresis is primarily attributed to traps at the channel/oxide interface as well as in the oxide. In this study, we present a physics-based self-consistent modeling framework to investigate the impact of border and interface traps on <span><math><mi>Δ</mi><msub><mi>V</mi><mi>h</mi></msub></math></span> and apply it to monolayer (1-L) MoS<sub>2</sub> field-effect transistors (FETs). The transient trapping and detrapping of charges during gate voltage sweeps across a wide range of frequencies and temperatures is analyzed using a two-state non-radiative multi-phonon (NMP) model. Our results reveal distinct dynamic responses for slow border and fast interface traps, with border traps exhibiting slower time constants due to larger relaxation energies and interface traps showing fast nuclear tunneling-dominated dynamics resulting from the smaller relaxation energies. These simulations highlights the critical role of the spatial and energetic distributions of the traps in determining <span><math><mi>Δ</mi><msub><mi>V</mi><mi>h</mi></msub></math></span>, providing insights into the stability of 2D FETs and paving the way for improved device engineering.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"299 ","pages":"Article 112333"},"PeriodicalIF":2.6,"publicationDate":"2025-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143609663","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-02-27DOI: 10.1016/j.mee.2025.112332
Linus Engelmann , IrenaeusWlokas
A deep-learning-based lithography model using a generative neural network (GAN) approach is developed and assessed for its ability to predict aerial images at different resist heights. The performance of the GAN approach is evaluated by analyzing deviations between model-generated aerial images and golden images, as well as differences in critical dimension (CD) values. Additionally, error analysis is conducted based on the feature distribution of each photomask. Selected patterns and their aerial images are compared both qualitatively to assess local errors and quantitatively through root-mean-square (RMS) errors to evaluate global accuracy. Error analysis reveals the features produced by the deep learning model leading to the highest deviation from the rigorous model results, and the error is decomposed into the error contributions of underpredicted and overpredicted features. An array of aerial images for selected resist heights produced by the deep learning model is assessed, revealing increasing errors with increasing resist heights. The limitations of applying deep learning techniques in computational lithography are illustrated by comparing a target pattern with and without optical proximity correction (OPC) features.
{"title":"On the feature accuracy of deep learning mask topography effect models","authors":"Linus Engelmann , IrenaeusWlokas","doi":"10.1016/j.mee.2025.112332","DOIUrl":"10.1016/j.mee.2025.112332","url":null,"abstract":"<div><div>A deep-learning-based lithography model using a generative neural network (GAN) approach is developed and assessed for its ability to predict aerial images at different resist heights. The performance of the GAN approach is evaluated by analyzing deviations between model-generated aerial images and golden images, as well as differences in critical dimension (CD) values. Additionally, error analysis is conducted based on the feature distribution of each photomask. Selected patterns and their aerial images are compared both qualitatively to assess local errors and quantitatively through root-mean-square (RMS) errors to evaluate global accuracy. Error analysis reveals the features produced by the deep learning model leading to the highest deviation from the rigorous model results, and the error is decomposed into the error contributions of underpredicted and overpredicted features. An array of aerial images for selected resist heights produced by the deep learning model is assessed, revealing increasing errors with increasing resist heights. The limitations of applying deep learning techniques in computational lithography are illustrated by comparing a target pattern with and without optical proximity correction (OPC) features.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"299 ","pages":"Article 112332"},"PeriodicalIF":2.6,"publicationDate":"2025-02-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143529001","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-02-25DOI: 10.1016/j.mee.2025.112331
Gerardo Gutierrez-Heredia , Ovidio Rodriguez-Lopez , Pedro Emanuel Rocha-Flores , Walter E. Voit
This study analyzed the electrical behavior of indium‑gallium‑zinc-oxide (IGZO) thin-film transistors (TFTs) under different applied voltages. The IGZO TFTs were fabricated on a polymer substrate using full photolithographic processes. The electrical performance was monitored under constant bias stress for 10,000 s and the analysis revealed relatively high field-effect mobility (>10 cm2/Vs) when higher voltages (>5 V) were applied to the IGZO TFTs. Furthermore, the experimental results demonstrated shifts in the threshold voltage (VTH), mobility, and saturation drain current, exhibiting a strong dependence on the applied voltage. After 10,000 s of bias stress, the threshold voltage shift varied by 0.5 V for the lowest applied voltage and exceeded 5 V for the higher values. Moreover, the electrical analysis indicated a significant reduction in the lifetime of IGZO TFTs when the applied voltage exceeded 15 V. These findings enable a comparative analysis of the impact of bias stress on mobility, VTH, and driving current, offering a pathway to optimize the electrical performance of TFTs-based flexible applications. Furthermore, by exploring the mechanism behind the changes induced by the constant electric field at the gate contact, this work provides insights for predicting the reliability and lifetime of novel devices tailored for wearable, flexible, and biomedical technologies.
{"title":"Impact of constant bias stress on reliability of IGZO thin-film transistors on softening polymer","authors":"Gerardo Gutierrez-Heredia , Ovidio Rodriguez-Lopez , Pedro Emanuel Rocha-Flores , Walter E. Voit","doi":"10.1016/j.mee.2025.112331","DOIUrl":"10.1016/j.mee.2025.112331","url":null,"abstract":"<div><div>This study analyzed the electrical behavior of indium‑gallium‑zinc-oxide (IGZO) thin-film transistors (TFTs) under different applied voltages. The IGZO TFTs were fabricated on a polymer substrate using full photolithographic processes. The electrical performance was monitored under constant bias stress for 10,000 s and the analysis revealed relatively high field-effect mobility (>10 cm<sup>2</sup>/Vs) when higher voltages (>5 V) were applied to the IGZO TFTs. Furthermore, the experimental results demonstrated shifts in the threshold voltage (V<sub>TH</sub>), mobility, and saturation drain current, exhibiting a strong dependence on the applied voltage. After 10,000 s of bias stress, the threshold voltage shift varied by 0.5 V for the lowest applied voltage and exceeded 5 V for the higher values. Moreover, the electrical analysis indicated a significant reduction in the lifetime of IGZO TFTs when the applied voltage exceeded 15 V. These findings enable a comparative analysis of the impact of bias stress on mobility, V<sub>TH</sub>, and driving current, offering a pathway to optimize the electrical performance of TFTs-based flexible applications. Furthermore, by exploring the mechanism behind the changes induced by the constant electric field at the gate contact, this work provides insights for predicting the reliability and lifetime of novel devices tailored for wearable, flexible, and biomedical technologies.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"298 ","pages":"Article 112331"},"PeriodicalIF":2.6,"publicationDate":"2025-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143512523","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-02-20DOI: 10.1016/j.mee.2025.112325
Hongbang Zhang , Miao Tian , Xiaokun Gu
Three-dimensional integrated circuits (3D ICs) have emerged at the forefront of semiconductor research due to their potential for enhancing performance and reducing power consumption. As semiconductor technology advances, the continuous miniaturization and increasing integration density of 3D ICs have made size and interface effects more pronounced, leading to higher heat flux densities and more complex thermal management challenges. Through‑silicon via (TSV) and back-end-of-line (BEOL) structures, as core components of 3D ICs, are responsible for horizontal and vertical interconnections and directly affect the thermal transport performance within the chip. In this review, we provide an overview of the current state of thermal management in TSVs and BEOL structures, discussing heat dissipation performance, thermal parameter extraction, structural optimization, and the development of layout algorithms. In response to the challenges of cross-scale simulations and the difficulty of characterizing the thermal properties and temperature distribution of complex micro-nano scale structures, the current state of theoretical calculations and thermal testing techniques at the micro-nano scale, which have been evolved as powerful tools in thermal management of 3D ICs, is also presented. This review summarizes the key advances and challenges in this field, highlighting the importance of addressing these issues to optimize TSVs and BEOL designs and enhance the thermal management performance of 3D ICs, providing valuable reference and guidance for future research.
{"title":"Thermal management of through-silicon vias and back-end-of-line layers in 3D ICs: A comprehensive review","authors":"Hongbang Zhang , Miao Tian , Xiaokun Gu","doi":"10.1016/j.mee.2025.112325","DOIUrl":"10.1016/j.mee.2025.112325","url":null,"abstract":"<div><div>Three-dimensional integrated circuits (3D ICs) have emerged at the forefront of semiconductor research due to their potential for enhancing performance and reducing power consumption. As semiconductor technology advances, the continuous miniaturization and increasing integration density of 3D ICs have made size and interface effects more pronounced, leading to higher heat flux densities and more complex thermal management challenges. Through‑silicon via (TSV) and back-end-of-line (BEOL) structures, as core components of 3D ICs, are responsible for horizontal and vertical interconnections and directly affect the thermal transport performance within the chip. In this review, we provide an overview of the current state of thermal management in TSVs and BEOL structures, discussing heat dissipation performance, thermal parameter extraction, structural optimization, and the development of layout algorithms. In response to the challenges of cross-scale simulations and the difficulty of characterizing the thermal properties and temperature distribution of complex micro-nano scale structures, the current state of theoretical calculations and thermal testing techniques at the micro-nano scale, which have been evolved as powerful tools in thermal management of 3D ICs, is also presented. This review summarizes the key advances and challenges in this field, highlighting the importance of addressing these issues to optimize TSVs and BEOL designs and enhance the thermal management performance of 3D ICs, providing valuable reference and guidance for future research.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"298 ","pages":"Article 112325"},"PeriodicalIF":2.6,"publicationDate":"2025-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143474091","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-02-20DOI: 10.1016/j.mee.2025.112324
Jesun Park , Seongwoo Kim , Taeyoung Cho , Myounggon Kang
This study proposes a low power read operation to minimize the hot carrier injection (HCI) phenomenon that occurs during read operations in 3D NAND Flash Memory. Owing to the characteristics of the 3D NAND Flash Memory structure, the channels of unselected strings can easily remain in a floating state. This leads to HCI during read operations, resulting in read disturbances. To improve the read disturb characteristics, triangular pulse voltages (VTP) with adjusted slopes and delayed application times were applied to the string selected line (SSL) and the ground selected line (GSL) during read operations. Using the proposed read scheme, it was confirmed that HCI was decreased compared to the conventional method, and it was possible to operate at low power.
{"title":"Optimization of read operation for low power consumption in 3D NAND flash memory","authors":"Jesun Park , Seongwoo Kim , Taeyoung Cho , Myounggon Kang","doi":"10.1016/j.mee.2025.112324","DOIUrl":"10.1016/j.mee.2025.112324","url":null,"abstract":"<div><div>This study proposes a low power read operation to minimize the hot carrier injection (HCI) phenomenon that occurs during read operations in 3D NAND Flash Memory. Owing to the characteristics of the 3D NAND Flash Memory structure, the channels of unselected strings can easily remain in a floating state. This leads to HCI during read operations, resulting in read disturbances. To improve the read disturb characteristics, triangular pulse voltages (V<sub>TP</sub>) with adjusted slopes and delayed application times were applied to the string selected line (SSL) and the ground selected line (GSL) during read operations. Using the proposed read scheme, it was confirmed that HCI was decreased compared to the conventional method, and it was possible to operate at low power.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"298 ","pages":"Article 112324"},"PeriodicalIF":2.6,"publicationDate":"2025-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143474092","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-02-17DOI: 10.1016/j.mee.2025.112330
Bishnu P. Khanal, Marlene Dugger
Defect reduction remains a critical objective in the integrated circuit manufacturing process, particularly within the highly re-entrant lithography modules where minimizing defects is crucial. Defects at the wafer edge can contaminate lithography modules and downstream processing equipment, leading to redistribution onto the wafer surface and adversely affecting overall device yield. A persistent challenge in the resist coating process is the formation of resist edge beads, driven by the strong Van der Waals attraction of excess photoresist (PR) to itself and the underlying substrate. The edge bead removal (EBR) process is a standard cleaning step designed to eliminate these edge beads and prevent potential contamination.
In this study, we identify the sources of EBR induced defects and additional EBR process encroachment toward edge patterning during the EBR cleaning process. This study provides a comprehensive study aimed at optimizing the EBR cleaning process to effectively eliminate EBR-induced defects, thereby enhancing overall device yield. Specifically, we identify three primary defects induced by the EBR cleaning process: rainbow-type, finger-shaped, and teardrop-type defects. Our experimental study reveals that in addition to EBR rinse time, PR cast time is crucial parameters contributing to the formation of these defects. By properly optimizing the PR cast time and EBR rinse time, we were able to remove nearly 100 % of dense clusters of defects that were easily visible even at low magnification optical microscopy throughout the wafer edge. We observed that shorter PR casting times shows edge defects caused by inefficient EBR process because of insufficient time for PR to fully settle causing superfluous PR to continue flowing toward wafer edge during EBR clearing step, leading to partial removal of PR at the wafer edge and the formation of rainbow defects. Proper optimization of both PR casting time and EBR chemistries dispense time is essential to resolve these defects, ensuring efficient EBR cleaning process and improved overall device yield.
{"title":"Optimization of edge bead removal (EBR) process to enhance defect reduction in optical lithography","authors":"Bishnu P. Khanal, Marlene Dugger","doi":"10.1016/j.mee.2025.112330","DOIUrl":"10.1016/j.mee.2025.112330","url":null,"abstract":"<div><div>Defect reduction remains a critical objective in the integrated circuit manufacturing process, particularly within the highly re-entrant lithography modules where minimizing defects is crucial. Defects at the wafer edge can contaminate lithography modules and downstream processing equipment, leading to redistribution onto the wafer surface and adversely affecting overall device yield. A persistent challenge in the resist coating process is the formation of resist edge beads, driven by the strong Van der Waals attraction of excess photoresist (PR) to itself and the underlying substrate. The edge bead removal (EBR) process is a standard cleaning step designed to eliminate these edge beads and prevent potential contamination.</div><div>In this study, we identify the sources of EBR induced defects and additional EBR process encroachment toward edge patterning during the EBR cleaning process. This study provides a comprehensive study aimed at optimizing the EBR cleaning process to effectively eliminate EBR-induced defects, thereby enhancing overall device yield. Specifically, we identify three primary defects induced by the EBR cleaning process: rainbow-type, finger-shaped, and teardrop-type defects. Our experimental study reveals that in addition to EBR rinse time, PR cast time is crucial parameters contributing to the formation of these defects. By properly optimizing the PR cast time and EBR rinse time, we were able to remove nearly 100 % of dense clusters of defects that were easily visible even at low magnification optical microscopy throughout the wafer edge. We observed that shorter PR casting times shows edge defects caused by inefficient EBR process because of insufficient time for PR to fully settle causing superfluous PR to continue flowing toward wafer edge during EBR clearing step, leading to partial removal of PR at the wafer edge and the formation of rainbow defects. Proper optimization of both PR casting time and EBR chemistries dispense time is essential to resolve these defects, ensuring efficient EBR cleaning process and improved overall device yield.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"298 ","pages":"Article 112330"},"PeriodicalIF":2.6,"publicationDate":"2025-02-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143444796","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-02-17DOI: 10.1016/j.mee.2025.112329
Zhang Zhang , Qifan Wang , Gang Shi , Gang Liu
In recent years, inspired by multifunctional image sensors, in-sensor computing technology that combines sensing and computing functions has become a new research hotspot in the field of machine vision, which is an extremely promising way to break through the Von Neumann architecture by equipping the sensing unit with the computing ability and avoiding the data moving in the computation process. Whereas most existing in-sensor computing systems can only realize the processing of spatial frames in-sensor and cannot fuse the time series information. In order to solve this limitation and realize the processing of time information and spatial frames in the sensor at the same time, it is necessary to decouple and process the information in the processing unit in the sensor. In this paper, a time series recognition neural network based on optoelectronic memristor arrays is proposed. By using the optical plasticity and relaxation effects of the optoelectronic memristor arrays and based on the in-sensor computing technology, the information timing decoupling, processing and recognition in the sensor are realized. The results show that the network achieves a time series recognition accuracy of 98.4 % with two frames of image input, and the recognition rate still reaches 90 % after weight quantization and the addition of 40 % noise.
{"title":"Neural network for in-sensor time series recognition based on optoelectronic memristor","authors":"Zhang Zhang , Qifan Wang , Gang Shi , Gang Liu","doi":"10.1016/j.mee.2025.112329","DOIUrl":"10.1016/j.mee.2025.112329","url":null,"abstract":"<div><div>In recent years, inspired by multifunctional image sensors, in-sensor computing technology that combines sensing and computing functions has become a new research hotspot in the field of machine vision, which is an extremely promising way to break through the Von Neumann architecture by equipping the sensing unit with the computing ability and avoiding the data moving in the computation process. Whereas most existing in-sensor computing systems can only realize the processing of spatial frames in-sensor and cannot fuse the time series information. In order to solve this limitation and realize the processing of time information and spatial frames in the sensor at the same time, it is necessary to decouple and process the information in the processing unit in the sensor. In this paper, a time series recognition neural network based on optoelectronic memristor arrays is proposed. By using the optical plasticity and relaxation effects of the optoelectronic memristor arrays and based on the in-sensor computing technology, the information timing decoupling, processing and recognition in the sensor are realized. The results show that the network achieves a time series recognition accuracy of 98.4 % with two frames of image input, and the recognition rate still reaches 90 % after weight quantization and the addition of 40 % noise.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"298 ","pages":"Article 112329"},"PeriodicalIF":2.6,"publicationDate":"2025-02-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143464427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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