Pub Date : 2025-12-05DOI: 10.1016/j.mee.2025.112436
Martin E.M. Loesener , Tobias Zinsler , Bernhard Stampfer , Florian Wimmer , Eleftherios Ioannidis , Walter Pflanzl , Rainer Minixhofer , Tibor Grasser , Michael Waltl
Advanced reliability simulators like Comphy capture much of the state-of-the-art modeling behind charge trapping processes. An alternative approach to Comphy is to apply stochastic models, e.g. the defect-centric model, directly to the experimental data to extract the impact of defects on the device behavior and trap densities. In order to efficiently design defect characterization experiments, however, it is of utmost importance to understand the robustness of the defect-centric model under a variety of pre-conditions. In this work, we evaluate the requirements to employ the defect-centric model for data analysis, using simulated data from Comphy based on a real 400 nm × 180 nm pMOS device. Our results show that the number of devices from wafer-level tests does not suffice for statistical evaluation of RTN analysis. Here, preferably array chips should be used. For BTI studies, both wafer-level and array-chip tests enable us to extract good estimates for defect parameters with little computational effort.
{"title":"Evaluation of the robustness of the defect-centric model for defect parameter extraction from RTN and BTI analysis using Comphy","authors":"Martin E.M. Loesener , Tobias Zinsler , Bernhard Stampfer , Florian Wimmer , Eleftherios Ioannidis , Walter Pflanzl , Rainer Minixhofer , Tibor Grasser , Michael Waltl","doi":"10.1016/j.mee.2025.112436","DOIUrl":"10.1016/j.mee.2025.112436","url":null,"abstract":"<div><div>Advanced reliability simulators like Comphy capture much of the state-of-the-art modeling behind charge trapping processes. An alternative approach to Comphy is to apply stochastic models, e.g. the defect-centric model, directly to the experimental data to extract the impact of defects on the device behavior and trap densities. In order to efficiently design defect characterization experiments, however, it is of utmost importance to understand the robustness of the defect-centric model under a variety of pre-conditions. In this work, we evaluate the requirements to employ the defect-centric model for data analysis, using simulated data from Comphy based on a real 400 nm × 180 nm pMOS device. Our results show that the number of devices from wafer-level tests does not suffice for statistical evaluation of RTN analysis. Here, preferably array chips should be used. For BTI studies, both wafer-level and array-chip tests enable us to extract good estimates for defect parameters with little computational effort.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"303 ","pages":"Article 112436"},"PeriodicalIF":3.1,"publicationDate":"2025-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145692374","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-29DOI: 10.1016/j.mee.2025.112428
F. Silva , L.-W. Ouyang , D.Y.C. Lie , C. Sweeney , J. Lopez
A fully-monolithic DC - 24 GHz SPDT (single-pole-double-throw) RF (radio-frequency) switch IC (integrated circuit) is designed and taped out in a 22 nm FD-SOI (fully-depleted silicon-on-insulator) CMOS process, targeting 5G FR1 and FR3 band applications. The first-generation switch (SW1) has measured insertion loss of about 1.9/2.8/3.8 dB at 10/18/24 GHz, reasonably close to the simulation data within 0.5 dB, and measured receive-antenna (RX-ANT) isolation of around 28.2/23.2/20.7 dB at 10/18/24 GHz. However, we found both the post-layout parasitic (PEX) RCC simulations (accounting for resistance, capacitance, and coupling capacitance) and the EM (electromagnetic) simulations underestimated the switch's insertion loss compared with measurement data, especially at frequencies above 30 GHz. To reduce this loss and to design a switch that may operate at the higher frequency FR2 band (i.e., 24.25–52.6 GHz), a second-generation switch (SW2) with improved transistor sizing and a matching network is proposed. PEX-RCC simulations indicate that the SW2 may reduce the insertion loss by up to ∼1 dB at 24 GHz vs. SW1, while maintaining the TX-RX isolation above 30 dB.
{"title":"A DC − 24 GHz SPDT switch design in 22 nm FD-SOI CMOS for 5G FR1 and FR3 bands","authors":"F. Silva , L.-W. Ouyang , D.Y.C. Lie , C. Sweeney , J. Lopez","doi":"10.1016/j.mee.2025.112428","DOIUrl":"10.1016/j.mee.2025.112428","url":null,"abstract":"<div><div>A fully-monolithic DC - 24 GHz SPDT (single-pole-double-throw) RF (radio-frequency) switch IC (integrated circuit) is designed and taped out in a 22 nm FD-SOI (fully-depleted silicon-on-insulator) CMOS process, targeting 5G FR1 and FR3 band applications. The first-generation switch (SW1) has measured insertion loss of about 1.9/2.8/3.8 dB at 10/18/24 GHz, reasonably close to the simulation data within 0.5 dB, and measured receive-antenna (RX-ANT) isolation of around 28.2/23.2/20.7 dB at 10/18/24 GHz. However, we found both the post-layout parasitic (PEX) RCC simulations (accounting for resistance, capacitance, and coupling capacitance) and the EM (electromagnetic) simulations underestimated the switch's insertion loss compared with measurement data, especially at frequencies above 30 GHz. To reduce this loss and to design a switch that may operate at the higher frequency FR2 band (i.e., 24.25–52.6 GHz), a second-generation switch (SW2) with improved transistor sizing and a matching network is proposed. PEX-RCC simulations indicate that the SW2 may reduce the insertion loss by up to ∼1 dB at 24 GHz vs. SW1, while maintaining the TX-RX isolation above 30 dB.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"303 ","pages":"Article 112428"},"PeriodicalIF":3.1,"publicationDate":"2025-11-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145623075","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-25DOI: 10.1016/j.mee.2025.112427
Jiejie Sun , Meining Ji , Hongguang Shen , Chuanpeng Jiang , Chao Wang , Meng Zhang , Kaihua Cao , Bi Wang , Haibo Ye
Data retention time, a crucial reliability parameter in spin-transfer torque magnetic random access memory (STT-MRAM), characterizes the capability to maintain stable data storage time. Methods for evaluating data retention time often face the issues of excessive test time and limited precision. This study investigates the data retention capability of STT-MRAM chips by using high-temperature acceleration and magnetic-field acceleration methods, which significantly enhance both testing efficiency and accuracy. The two acceleration methods show high consistency in predicting EBmeff and Δeff, with a relative deviation of only 10 % at −25 °C. Furthermore, the observed dependence of EBeff on the magnetic field aligns well with theoretical predictions derived from the domain wall model. Experimental results show that STT-MRAM chips can achieve a data retention time exceeding 20 years at 105 °C, fulfilling the stringent reliability criteria required for industrial-grade memory applications. These findings provide critical experimental verification and technical insights to support the integration of STT-MRAM into next-generation memory architectures.
{"title":"Research on evaluation method of data retention capability of STT-MRAM chips","authors":"Jiejie Sun , Meining Ji , Hongguang Shen , Chuanpeng Jiang , Chao Wang , Meng Zhang , Kaihua Cao , Bi Wang , Haibo Ye","doi":"10.1016/j.mee.2025.112427","DOIUrl":"10.1016/j.mee.2025.112427","url":null,"abstract":"<div><div>Data retention time, a crucial reliability parameter in spin-transfer torque magnetic random access memory (STT-MRAM), characterizes the capability to maintain stable data storage time. Methods for evaluating data retention time often face the issues of excessive test time and limited precision. This study investigates the data retention capability of STT-MRAM chips by using high-temperature acceleration and magnetic-field acceleration methods, which significantly enhance both testing efficiency and accuracy. The two acceleration methods show high consistency in predicting <em>E</em><sub>Bmeff</sub> and <em>Δ</em><sub>eff</sub>, with a relative deviation of only 10 % at −25 °C. Furthermore, the observed dependence of <em>E</em><sub>Beff</sub> on the magnetic field aligns well with theoretical predictions derived from the domain wall model. Experimental results show that STT-MRAM chips can achieve a data retention time exceeding 20 years at 105 °C, fulfilling the stringent reliability criteria required for industrial-grade memory applications. These findings provide critical experimental verification and technical insights to support the integration of STT-MRAM into next-generation memory architectures.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"303 ","pages":"Article 112427"},"PeriodicalIF":3.1,"publicationDate":"2025-11-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145623074","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Spiking Neural Networks (SNNs) inspired by the human brain are promising alternative to solve real-life complex problems, such as pattern recognition at low energy consumption. A key approach to implementing SNNs involves using a Resistance Random Access Memory (RRAM) crossbar array to simulate synaptic weights, which can have multi-step resistance states suitable for processing analog signals. However, a major hurdle with traditional 2-terminal RRAMs is the “read–write dilemma”: the low voltage needed for a non-destructive read operation conflicts with the high voltage required for a write operation, making simultaneous, real-time learning challenging. Current solutions to this problem, such as time or frequency division multiplexing and separate read/write arrays, increase the circuit’s complexity, size, or operation time. This paper proposes a novel solution using a recently developed 3-terminal (3T) (PCMO) RRAM. By using two terminals for writing and a third, dedicated decoupled terminal for reading, this architecture allows for simultaneous and asynchronous read and write operations. This approach resolves the read–write conflict inherent in 2-terminal designs, enabling real-time learning in SNNs without significant increase in circuit overhead and learning time.
{"title":"Asynchronous real-time learning in Spiking Neural Network using 3-terminal Resistance Random Access Memory","authors":"Harshvardhan Singh , Nirmal Solanki , Jaskirat Singh Maskeen , Shalu Saini , Madhav Pathak , Sandip Lashkare","doi":"10.1016/j.mee.2025.112429","DOIUrl":"10.1016/j.mee.2025.112429","url":null,"abstract":"<div><div>Spiking Neural Networks (SNNs) inspired by the human brain are promising alternative to solve real-life complex problems, such as pattern recognition at low energy consumption. A key approach to implementing SNNs involves using a Resistance Random Access Memory (RRAM) crossbar array to simulate synaptic weights, which can have multi-step resistance states suitable for processing analog signals. However, a major hurdle with traditional 2-terminal RRAMs is the “read–write dilemma”: the low voltage needed for a non-destructive read operation conflicts with the high voltage required for a write operation, making simultaneous, real-time learning challenging. Current solutions to this problem, such as time or frequency division multiplexing and separate read/write arrays, increase the circuit’s complexity, size, or operation time. This paper proposes a novel solution using a recently developed 3-terminal (3T) <span><math><mrow><msub><mrow><mtext>Pr</mtext></mrow><mrow><mn>0</mn><mo>.</mo><mn>7</mn></mrow></msub><msub><mrow><mtext>Ca</mtext></mrow><mrow><mn>0</mn><mo>.</mo><mn>3</mn></mrow></msub><msub><mrow><mtext>MnO</mtext></mrow><mrow><mn>3</mn></mrow></msub></mrow></math></span> (PCMO) RRAM. By using two terminals for writing and a third, dedicated decoupled terminal for reading, this architecture allows for simultaneous and asynchronous read and write operations. This approach resolves the read–write conflict inherent in 2-terminal designs, enabling real-time learning in SNNs without significant increase in circuit overhead and learning time.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"303 ","pages":"Article 112429"},"PeriodicalIF":3.1,"publicationDate":"2025-11-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145622910","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-06DOI: 10.1016/j.mee.2025.112426
M. Bendra , W. Goes , S. Selberherr , V. Sverdlov
The reliability of multilayered spin-transfer torque magnetoresistive random access memory with synthetic antiferromagnets is crucial for computing-in-memory architectures, high-performance computing, and high-density storage applications. This study investigates the role of interlayer exchange coupling in magnetic tunnel junction structures, which are fundamental to spin-transfer torque magnetoresistive random access memory performance and stability. We analyze how interlayer exchange coupling influences magnetic stability and spin-transfer torque switching efficiency using finite element method simulations combined with the Landau–Lifshitz–Gilbert equation. Our findings reveal that optimizing interlayer exchange coupling not only enhances data retention and write/read speeds but also mitigates miniaturization challenges and improves device reliability in downscaled spin-transfer torque magnetoresistive random access memory technologies. The results further emphasize the strong dependence of interlayer exchange coupling on spacer properties, which dictate magnetic orientations and coupling energy, offering a strategic pathway to engineer more efficient and robust spin-transfer torque magnetoresistive random access memory devices. This work highlights the critical impact of magnetic coupling on the switching dynamics and long-term stability of spintronic memory, providing insights that pave the way for next-generation, high-performance memory solutions.
{"title":"Simulation of SAF-enhanced multilayered STT-MRAM structures","authors":"M. Bendra , W. Goes , S. Selberherr , V. Sverdlov","doi":"10.1016/j.mee.2025.112426","DOIUrl":"10.1016/j.mee.2025.112426","url":null,"abstract":"<div><div>The reliability of multilayered spin-transfer torque magnetoresistive random access memory with synthetic antiferromagnets is crucial for computing-in-memory architectures, high-performance computing, and high-density storage applications. This study investigates the role of interlayer exchange coupling in magnetic tunnel junction structures, which are fundamental to spin-transfer torque magnetoresistive random access memory performance and stability. We analyze how interlayer exchange coupling influences magnetic stability and spin-transfer torque switching efficiency using finite element method simulations combined with the Landau–Lifshitz–Gilbert equation. Our findings reveal that optimizing interlayer exchange coupling not only enhances data retention and write/read speeds but also mitigates miniaturization challenges and improves device reliability in downscaled spin-transfer torque magnetoresistive random access memory technologies. The results further emphasize the strong dependence of interlayer exchange coupling on spacer properties, which dictate magnetic orientations and coupling energy, offering a strategic pathway to engineer more efficient and robust spin-transfer torque magnetoresistive random access memory devices. This work highlights the critical impact of magnetic coupling on the switching dynamics and long-term stability of spintronic memory, providing insights that pave the way for next-generation, high-performance memory solutions.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"302 ","pages":"Article 112426"},"PeriodicalIF":3.1,"publicationDate":"2025-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145465428","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
On-chip transformers are fundamental components in integrated circuits, serving key functions such as impedance matching, signal coupling, voltage conversion, and galvanic isolation in high-frequency and mixed-signal systems. However, their performance is often limited by factors like substrate losses, interwinding capacitance, and series resistance, which reduce both bandwidth and efficiency. This paper presents a novel non-spiral, vialess stacked on-chip transformer featuring a compact 620 μm × 620 μm footprint, utilizing only two metal layers to achieve enhanced high-frequency power transfer efficiency. Key performance metrics, such as quality factor (Q), coupling coefficient (Kim), self-resonant frequency, and maximum power transfer efficiency, are compared against those of interleaved and interwinding transformers, all under identical geometric constraints, using both experimental measurements and electromagnetic simulations. All devices were fabricated on a high-resistivity silicon substrate with a trap-rich layer (HR-Si + TR), providing a quasi-insulated platform that significantly reduces substrate losses. Despite the interwinding transformer achieving the highest coupling coefficient (Kim = 0.96) and the interleaved transformer showing superior Q-factors (Q1 = Q2 = 5.7), the proposed non-spiral stacked design demonstrates the larger peak power transfer efficiency of 0.72 at 2.5 GHz, outperforming the interleaved (0.60 at 2.66 GHz) and interwinding (0.45 at 0.90 GHz) configurations. Moreover, the design maintains this performance superiority even on standard low-resistivity silicon, confirming its robustness and suitability for passive RF integration in CMOS-compatible processes. This efficiency enhancement stems from an exceptionally low mutual resistive coupling, achieved through strong vertical magnetic linkage and reduced series resistance in parallel conductor paths.
{"title":"Vialess non-spiral on-chip stacked transformer on high-resistivity silicon for improved RF power transfer efficiency","authors":"Najeh Zeidi , Farès Tounsi , Jean-Pierre Raskin , Denis Flandre","doi":"10.1016/j.mee.2025.112424","DOIUrl":"10.1016/j.mee.2025.112424","url":null,"abstract":"<div><div>On-chip transformers are fundamental components in integrated circuits, serving key functions such as impedance matching, signal coupling, voltage conversion, and galvanic isolation in high-frequency and mixed-signal systems. However, their performance is often limited by factors like substrate losses, interwinding capacitance, and series resistance, which reduce both bandwidth and efficiency. This paper presents a novel non-spiral, vialess stacked on-chip transformer featuring a compact 620 μm × 620 μm footprint, utilizing only two metal layers to achieve enhanced high-frequency power transfer efficiency. Key performance metrics, such as quality factor (<em>Q</em>), coupling coefficient (<em>K</em><sub><em>im</em></sub>), self-resonant frequency, and maximum power transfer efficiency, are compared against those of interleaved and interwinding transformers, all under identical geometric constraints, using both experimental measurements and electromagnetic simulations. All devices were fabricated on a high-resistivity silicon substrate with a trap-rich layer (HR-Si + TR), providing a quasi-insulated platform that significantly reduces substrate losses. Despite the interwinding transformer achieving the highest coupling coefficient (<em>K</em><sub><em>im</em></sub> = 0.96) and the interleaved transformer showing superior <em>Q</em>-factors (<em>Q</em><sub><em>1</em></sub> = <em>Q</em><sub><em>2</em></sub> = 5.7), the proposed non-spiral stacked design demonstrates the larger peak power transfer efficiency of 0.72 at 2.5 GHz, outperforming the interleaved (0.60 at 2.66 GHz) and interwinding (0.45 at 0.90 GHz) configurations. Moreover, the design maintains this performance superiority even on standard low-resistivity silicon, confirming its robustness and suitability for passive RF integration in CMOS-compatible processes. This efficiency enhancement stems from an exceptionally low mutual resistive coupling, achieved through strong vertical magnetic linkage and reduced series resistance in parallel conductor paths.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"302 ","pages":"Article 112424"},"PeriodicalIF":3.1,"publicationDate":"2025-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145465430","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-03DOI: 10.1016/j.mee.2025.112421
Moritz Tockner , Moritz Stockinger , Oliver Lang , Andreas Meingassner , Mario Huemer
In wireless communications, in-phase (I) and quadrature-phase (Q) imbalance is a well-understood issue, and an extensive body of different I/Q imbalance estimation and compensation algorithms exists in the literature. Many of these algorithms, including those in this work, focus on mitigating I/Q imbalance on the receiver side. We consider frequency-independent (FID) estimators that operate as so-called blind algorithms, where little to no knowledge about the transmitted data is required. However, little effort has been made to compare the required resources for implementing these algorithms in hardware. In this work, we compare a comprehensive list of such algorithms with regard to their logic utilization, required registers, and embedded multipliers when implementing them on a field-programmable gate array (FPGA). Subsequently, we provide synthesis results based on the SkyWater 130 nm open-source process design kit (PDK), which enables comparisons of the required chip areas for the corresponding application-specific integrated circuit (ASIC) designs. We optimize the fixed-point bit-widths, and other hardware implementation specific parameters of the individual estimators to provide meaningful results. This optimization aims to achieve a common performance target for a typical orthogonal frequency-division multiplexing (OFDM) signal scenario.
{"title":"Extensive FPGA and ASIC resource comparison for blind I/Q imbalance estimators and compensators","authors":"Moritz Tockner , Moritz Stockinger , Oliver Lang , Andreas Meingassner , Mario Huemer","doi":"10.1016/j.mee.2025.112421","DOIUrl":"10.1016/j.mee.2025.112421","url":null,"abstract":"<div><div>In wireless communications, in-phase (I) and quadrature-phase (Q) imbalance is a well-understood issue, and an extensive body of different I/Q imbalance estimation and compensation algorithms exists in the literature. Many of these algorithms, including those in this work, focus on mitigating I/Q imbalance on the receiver side. We consider frequency-independent (FID) estimators that operate as so-called blind algorithms, where little to no knowledge about the transmitted data is required. However, little effort has been made to compare the required resources for implementing these algorithms in hardware. In this work, we compare a comprehensive list of such algorithms with regard to their logic utilization, required registers, and embedded multipliers when implementing them on a field-programmable gate array (FPGA). Subsequently, we provide synthesis results based on the SkyWater 130<!--> <!-->nm open-source process design kit (PDK), which enables comparisons of the required chip areas for the corresponding application-specific integrated circuit (ASIC) designs. We optimize the fixed-point bit-widths, and other hardware implementation specific parameters of the individual estimators to provide meaningful results. This optimization aims to achieve a common performance target for a typical orthogonal frequency-division multiplexing (OFDM) signal scenario.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"302 ","pages":"Article 112421"},"PeriodicalIF":3.1,"publicationDate":"2025-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145465427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Localized defects in the edges of top gate insulators present a serious obstacle for scaling of field-effect transistors (FETs) with 2D channels. However, most experimental studies of their bias stability are performed on micron-scale prototypes. In these devices homogeneous trap distributions can be assumed since the edges are negligible as compared to the channel lengths, and thus their bias stability is mostly determined by the energy barrier between the oxide defect bands and the conduction band edge of the channel (for n-FETs). By doing technology computer aided design (TCAD) modeling for nanoscale MoS/HfO FETs with edge trap distributions, here we for the first time demonstrate that the hysteresis and positive bias-temperature instabilities (PBTI) may strongly depend on the Fermi level pinning, type of S/D contact and top gate scaling. As a result, even favorable alignment of oxide defect bands with respect to the channel conduction band edge may result in poor bias stability and vice versa. With these findings we open a pathway towards reliability-aware design of scalable 2D electronics which is currently disregarded by the industry.
{"title":"Understanding the impact of contacts and top gate scaling on the reliability of nanoscale MoS2 FETs by TCAD modeling","authors":"Yezhu Lv, Yajing Chai, Yehao Wu, Yury Yu. Illarionov","doi":"10.1016/j.mee.2025.112425","DOIUrl":"10.1016/j.mee.2025.112425","url":null,"abstract":"<div><div>Localized defects in the edges of top gate insulators present a serious obstacle for scaling of field-effect transistors (FETs) with 2D channels. However, most experimental studies of their bias stability are performed on micron-scale prototypes. In these devices homogeneous trap distributions can be assumed since the edges are negligible as compared to the channel lengths, and thus their bias stability is mostly determined by the energy barrier between the oxide defect bands and the conduction band edge of the channel (for n-FETs). By doing technology computer aided design (TCAD) modeling for nanoscale MoS<span><math><msub><mrow></mrow><mrow><mn>2</mn></mrow></msub></math></span>/HfO<span><math><msub><mrow></mrow><mrow><mn>2</mn></mrow></msub></math></span> FETs with edge trap distributions, here we for the first time demonstrate that the hysteresis and positive bias-temperature instabilities (PBTI) may strongly depend on the Fermi level pinning, type of S/D contact and top gate scaling. As a result, even favorable alignment of oxide defect bands with respect to the channel conduction band edge may result in poor bias stability and vice versa. With these findings we open a pathway towards reliability-aware design of scalable 2D electronics which is currently disregarded by the industry.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"302 ","pages":"Article 112425"},"PeriodicalIF":3.1,"publicationDate":"2025-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145465429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-27DOI: 10.1016/j.mee.2025.112423
Francisco J. Romero, Víctor Toral, Diego P. Morales, Noel Rodríguez
Memcapacitors, due to their variable capacitance and non-volatile memory effect, are expected to cause a disruption across different areas of research and engineering. In the context of power electronics, memcapacitors have not yet been considered despite their potential for ripple reduction, voltage stabilization and improved energy efficiency. This work presents both simulation and experimental results demonstrating how incorporating a memcapacitor at the output of a DC-DC buck converter can significantly reduce the output voltage ripple. We first propose and validate a memcapacitor emulator that can be implemented using off-the-shelf components. After that, the memcapacitor emulator is used to study the output voltage ripple in the permanent regime of a DC-DC buck converter as well as its effect on the transient response. The results demonstrate that the use of a charge-controlled memcapacitor can reduce the output voltage ripple by up to 90 %. While the memcapacitor emulator serves as a practical tool for this investigation, the goal of this work is demonstrating the potential of memcapacitors for power electronics, evidencing the need for further research and development toward solid-state memcapacitor devices to unlock new possibilities for ripple reduction, energy efficiency, and voltage stabilization in advanced power electronics systems.
{"title":"Charge-controlled memcapacitors for the output voltage ripple reduction in DC-DC buck converters","authors":"Francisco J. Romero, Víctor Toral, Diego P. Morales, Noel Rodríguez","doi":"10.1016/j.mee.2025.112423","DOIUrl":"10.1016/j.mee.2025.112423","url":null,"abstract":"<div><div>Memcapacitors, due to their variable capacitance and non-volatile memory effect, are expected to cause a disruption across different areas of research and engineering. In the context of power electronics, memcapacitors have not yet been considered despite their potential for ripple reduction, voltage stabilization and improved energy efficiency. This work presents both simulation and experimental results demonstrating how incorporating a memcapacitor at the output of a DC-DC buck converter can significantly reduce the output voltage ripple. We first propose and validate a memcapacitor emulator that can be implemented using off-the-shelf components. After that, the memcapacitor emulator is used to study the output voltage ripple in the permanent regime of a DC-DC buck converter as well as its effect on the transient response. The results demonstrate that the use of a charge-controlled memcapacitor can reduce the output voltage ripple by up to 90 %. While the memcapacitor emulator serves as a practical tool for this investigation, the goal of this work is demonstrating the potential of memcapacitors for power electronics, evidencing the need for further research and development toward solid-state memcapacitor devices to unlock new possibilities for ripple reduction, energy efficiency, and voltage stabilization in advanced power electronics systems.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"302 ","pages":"Article 112423"},"PeriodicalIF":3.1,"publicationDate":"2025-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145417026","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-13DOI: 10.1016/j.mee.2025.112420
Guoqiang Zhao , Yi Zhao
Hybrid bonding technology is widely concerned in the field of advanced packaging, due to its high density and short distance. Current research focuses on the implementation of wafers with only one type of pad. However, integrating multi-type pads on the same wafer introduces huge challenges in process control, especially ensuring tight concave variations across all copper pads during the CMP step. In this work, the novel hybrid bonding process for wafers featuring pads of various sizes and shapes has been developed and verified. Characterization techniques such as AFM, SEM, TEM and EDS were adopted to conduct in-depth analysis of the interest region before and after bonding, confirming the effectiveness of the strategy. These results can provide guidance for flexibilizing pad design, optimizing bonding process, and enhancing bonding quality under complex scenarios.
{"title":"Process development and integration of hybrid bonding for wafers with multi-type bonding pads","authors":"Guoqiang Zhao , Yi Zhao","doi":"10.1016/j.mee.2025.112420","DOIUrl":"10.1016/j.mee.2025.112420","url":null,"abstract":"<div><div>Hybrid bonding technology is widely concerned in the field of advanced packaging, due to its high density and short distance. Current research focuses on the implementation of wafers with only one type of pad. However, integrating multi-type pads on the same wafer introduces huge challenges in process control, especially ensuring tight concave variations across all copper pads during the CMP step. In this work, the novel hybrid bonding process for wafers featuring pads of various sizes and shapes has been developed and verified. Characterization techniques such as AFM, SEM, TEM and EDS were adopted to conduct in-depth analysis of the interest region before and after bonding, confirming the effectiveness of the strategy. These results can provide guidance for flexibilizing pad design, optimizing bonding process, and enhancing bonding quality under complex scenarios.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"302 ","pages":"Article 112420"},"PeriodicalIF":3.1,"publicationDate":"2025-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145321083","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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