Microelectronic Engineering最新文献

Variation-robust CMOS monostable multivibrator-based spiking neuron and spiking neural networks 基于变鲁棒CMOS单稳态多振子的脉冲神经元和脉冲神经网络

IF 3.1 4区工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronic Engineering

Pub Date : 2026-06-01 Epub Date: 2026-01-12 DOI: 10.1016/j.mee.2025.112444

Maleeha Abdul Azeez, Dhanaraj K.J.

Spiking Neural Networks (SNNs) are a class of Artificial Neural Networks (ANNs) that process information encoded in spike trains. Hardware implementations of spiking neurons, the building blocks of SNNs, reveal that SNNs can be realized as low-power and high-density neural networks. In this work, a spiking neuron design realized using a CMOS-based monostable multivibrator circuit is proposed. Performance comparisons with similar spiking neuron designs show that the proposed neuron exhibits high robustness to hardware variations in addition to its low power, low area, and low latency characteristics. The ability to operate over a wide range of spike rates enables deployment of the neuron in a wide variety of applications. SNNs using rate encoding and TTFS (Time-To-First-Spike) encoding designed with the proposed neuron exhibit better performance results in comparison with those realized using other similar designs in the simulation studies. The possibility of using the neuron for large-scale SNNs is also explored. Post-layout simulations of the neuron and two SNNs built with the neuron also show high robustness, conforming with the corresponding results from the pre-layout simulations. With an active footprint area of

33 μ m^{2}

and energy per spike as low as 100 fJ, the monostable multivibrator-based neuron proves to be a simple, compact, energy-efficient and variation-tolerant spiking neuron, which is a good candidate for building diverse SNNs.

尖峰神经网络（SNNs）是一类处理编码在尖峰序列中的信息的人工神经网络（ann）。snn的构建模块尖峰神经元的硬件实现表明snn可以实现低功耗和高密度的神经网络。本文提出了一种基于cmos的单稳态多振器电路实现的尖峰神经元设计。与类似峰值神经元设计的性能比较表明，所提出的神经元除了具有低功耗、低面积和低延迟特性外，还具有对硬件变化的高鲁棒性。在大范围的尖峰速率范围内工作的能力使神经元能够在各种各样的应用中部署。采用速率编码和TTFS （Time-To-First-Spike）编码的snn在仿真研究中比使用其他类似设计实现的snn表现出更好的性能结果。还探讨了将该神经元用于大规模snn的可能性。该神经元的布局后仿真和用该神经元构建的两个snn也显示出较高的鲁棒性，与布局前仿真的结果一致。基于单稳态多振子的神经元具有简单、紧凑、节能和耐变化的特点，有效占地面积为33μm2，每尖峰能量低至100 fJ，是构建多种snn的理想选择。

{"title":"Variation-robust CMOS monostable multivibrator-based spiking neuron and spiking neural networks","authors":"Maleeha Abdul Azeez, Dhanaraj K.J.","doi":"10.1016/j.mee.2025.112444","DOIUrl":"10.1016/j.mee.2025.112444","url":null,"abstract":"<div><div>Spiking Neural Networks (SNNs) are a class of Artificial Neural Networks (ANNs) that process information encoded in spike trains. Hardware implementations of spiking neurons, the building blocks of SNNs, reveal that SNNs can be realized as low-power and high-density neural networks. In this work, a spiking neuron design realized using a CMOS-based monostable multivibrator circuit is proposed. Performance comparisons with similar spiking neuron designs show that the proposed neuron exhibits high robustness to hardware variations in addition to its low power, low area, and low latency characteristics. The ability to operate over a wide range of spike rates enables deployment of the neuron in a wide variety of applications. SNNs using rate encoding and TTFS (Time-To-First-Spike) encoding designed with the proposed neuron exhibit better performance results in comparison with those realized using other similar designs in the simulation studies. The possibility of using the neuron for large-scale SNNs is also explored. Post-layout simulations of the neuron and two SNNs built with the neuron also show high robustness, conforming with the corresponding results from the pre-layout simulations. With an active footprint area of <span><math><mrow><mn>33</mn><mspace></mspace><mi>μ</mi><msup><mrow><mi>m</mi></mrow><mrow><mn>2</mn></mrow></msup></mrow></math></span> and energy per spike as low as 100 fJ, the monostable multivibrator-based neuron proves to be a simple, compact, energy-efficient and variation-tolerant spiking neuron, which is a good candidate for building diverse SNNs.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"304 ","pages":"Article 112444"},"PeriodicalIF":3.1,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145978972","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A product qualification vehicle (PQV) for accelerated yield learning and efficient fault isolation in 28 nm HKMG technologies by capturing LDE and BEOL weak patterns 通过捕获LDE和BEOL弱模式，在28nm HKMG技术中加速良率学习和有效故障隔离的产品认证工具（PQV）

IF 3.1 4区工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronic Engineering

Pub Date : 2026-06-01 Epub Date: 2026-01-21 DOI: 10.1016/j.mee.2026.112452

Enjing Cai , Limin Zhou , Qiang Chen , David Wei Zhang , Qingqing Sun , Hao Zhu

As CMOS technology scales to the 28 nm node and beyond, systematic yield limiters such as layout-dependent effects (LDE) and back-end-of-line (BEOL) weak patterns induced by routing congestion become increasingly pronounced. This creates a significant “SRAM-to-Product” gap, where conventional static random-access memory (SRAM)-based process monitoring inadequately reflects actual product performance. Moreover, the inherent time-consuming and resource-intensive nature of failure analysis (FA) for product-like monitors, primarily due to their dependency on complex electronic design automation (EDA)-based diagnostics, constitutes a severe FA bottleneck. In this paper, we present a novel product qualification vehicle (PQV), implemented on a 28 nm high-k/metal gate (HKMG) platform, that effectively bridges this critical gap. The PQV incorporates dedicated arrays of bit-cells constructed from standard logic gates, strategically designed to authentically replicate product-level LDE and BEOL stressors through a realistic place & route (P&R) flow. Crucially, it features an EDA-less diagnostic engine that provides direct physical coordinates of failing bits, thereby streamlining fault isolation by completely eliminating the need for conventional EDA tools. Silicon validation demonstrates that the PQV successfully captures critical LDE-induced functional failures and BEOL via-open defects systematically missed by conventional SRAMs. This methodology accelerates the fault-to-physical root-cause diagnosis cycle by over twelve times, facilitating rapid process learning and substantially reducing time-to-market.

随着CMOS技术扩展到28纳米及以上节点，布线依赖效应（LDE）和路由拥塞引起的后端线（BEOL）弱模式等系统良率限制变得越来越明显。这造成了一个显著的“SRAM到产品”的差距，传统的基于静态随机存取存储器（SRAM）的过程监控不能充分反映实际的产品性能。此外，类产品显示器的故障分析（FA）固有的耗时和资源密集型性质，主要是由于它们依赖于基于复杂电子设计自动化（EDA）的诊断，构成了严重的故障分析瓶颈。在本文中，我们提出了一种新的产品认证工具（PQV），在28纳米高k/金属栅极（HKMG）平台上实现，有效地弥补了这一关键差距。PQV集成了由标准逻辑门构成的专用位单元阵列，通过现实的位置路径（P&；R）流，可以真实地复制产品级LDE和BEOL压力源。最重要的是，它具有一个不需要EDA的诊断引擎，可以提供故障位的直接物理坐标，从而通过完全消除对传统EDA工具的需求来简化故障隔离。硅验证表明，PQV成功捕获了由lde引起的关键功能故障和BEOL，这是传统sram系统无法通过的开放缺陷。这种方法将故障到物理根本原因诊断周期加快了12倍以上，促进了快速流程学习并大大缩短了上市时间。

{"title":"A product qualification vehicle (PQV) for accelerated yield learning and efficient fault isolation in 28 nm HKMG technologies by capturing LDE and BEOL weak patterns","authors":"Enjing Cai , Limin Zhou , Qiang Chen , David Wei Zhang , Qingqing Sun , Hao Zhu","doi":"10.1016/j.mee.2026.112452","DOIUrl":"10.1016/j.mee.2026.112452","url":null,"abstract":"<div><div>As CMOS technology scales to the 28 nm node and beyond, systematic yield limiters such as layout-dependent effects (LDE) and back-end-of-line (BEOL) weak patterns induced by routing congestion become increasingly pronounced. This creates a significant “SRAM-to-Product” gap, where conventional static random-access memory (SRAM)-based process monitoring inadequately reflects actual product performance. Moreover, the inherent time-consuming and resource-intensive nature of failure analysis (FA) for product-like monitors, primarily due to their dependency on complex electronic design automation (EDA)-based diagnostics, constitutes a severe FA bottleneck. In this paper, we present a novel product qualification vehicle (PQV), implemented on a 28 nm high-k/metal gate (HKMG) platform, that effectively bridges this critical gap. The PQV incorporates dedicated arrays of bit-cells constructed from standard logic gates, strategically designed to authentically replicate product-level LDE and BEOL stressors through a realistic place & route (P&R) flow. Crucially, it features an EDA-less diagnostic engine that provides direct physical coordinates of failing bits, thereby streamlining fault isolation by completely eliminating the need for conventional EDA tools. Silicon validation demonstrates that the PQV successfully captures critical LDE-induced functional failures and BEOL via-open defects systematically missed by conventional SRAMs. This methodology accelerates the fault-to-physical root-cause diagnosis cycle by over twelve times, facilitating rapid process learning and substantially reducing time-to-market.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"304 ","pages":"Article 112452"},"PeriodicalIF":3.1,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146090391","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A new subthreshold half-select free SRAM with dynamic feedback cut-off for low-power and high speed applications 具有动态反馈截止的新型亚阈值半选择自由SRAM，适用于低功耗和高速应用

IF 3.1 4区工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronic Engineering

Pub Date : 2026-06-01 Epub Date: 2026-01-01 DOI: 10.1016/j.mee.2025.112438

Mohammadhasan jali , S. Mohammadali Zanjani , Mehdi Dolatshahi , Behrang Barekatain

This paper presents a novel 10 T static random-access memory (SRAM) cell designed for low-power, high-speed, and half-selected disturbance-free applications, featuring a differential write operation and a separated single-ended read operation. To reduce power consumption and enhance write stability, one of the back-to-back inverters is dynamically based on bit line value, removed from the circuit during the write phase, without the need for auxiliary circuitry. This functionality is implemented using stacked transistors in a single inverter, which also reduces leakage power. Moreover, subthreshold operation, along with dynamic threshold techniques, is employed to achieve additional power reduction. The proposed cell is evaluated through HSPICE simulations using 32 nm carbon nanotube field-effect transistor (CNFET) technology. Monte Carlo analysis shows that the write margin (WM), read static noise margin (RSNM), and hold static noise margin (HSNM) are 139.9 mV, 65.4 mV, and 63.9 mV, respectively. The write and read access times are 228.2 ps and 209.8 ps, respectively. The maximum write power consumption is 3.8 nW, while the read and leakage power are 10.4 nW and 252.2 pW, respectively. The minimum operating voltage is 150 mV, with an RSNM of 26 mV. The proposed 10 T SRAM cell occupies an area of about 0.161 μm².

本文提出了一种新颖的10t静态随机存取存储器（SRAM）单元，设计用于低功耗，高速和半选择无干扰应用，具有差分写入操作和分离的单端读取操作。为了降低功耗和提高写入稳定性，其中一个背靠背逆变器是动态地基于位线值的，在写入阶段从电路中移除，而不需要辅助电路。该功能是在单个逆变器中使用堆叠晶体管实现的，这也减少了泄漏功率。此外，采用亚阈值操作以及动态阈值技术来实现额外的功耗降低。采用32纳米碳纳米管场效应晶体管（CNFET）技术，通过HSPICE模拟对所提出的电池进行了评估。蒙特卡罗分析表明，写入余量（WM）、读取静态噪声余量（RSNM）和保持静态噪声余量（HSNM）分别为139.9 mV、65.4 mV和63.9 mV。写和读访问时间分别为228.2 ps和209.8 ps。最大写功耗3.8 nW，最大读功耗10.4 nW，最大漏功耗252.2 pW。最小工作电压为150mv， RSNM为26mv。所提出的10 T SRAM单元占地约0.161 μm2。

{"title":"A new subthreshold half-select free SRAM with dynamic feedback cut-off for low-power and high speed applications","authors":"Mohammadhasan jali , S. Mohammadali Zanjani , Mehdi Dolatshahi , Behrang Barekatain","doi":"10.1016/j.mee.2025.112438","DOIUrl":"10.1016/j.mee.2025.112438","url":null,"abstract":"<div><div>This paper presents a novel 10 T static random-access memory (SRAM) cell designed for low-power, high-speed, and half-selected disturbance-free applications, featuring a differential write operation and a separated single-ended read operation. To reduce power consumption and enhance write stability, one of the back-to-back inverters is dynamically based on bit line value, removed from the circuit during the write phase, without the need for auxiliary circuitry. This functionality is implemented using stacked transistors in a single inverter, which also reduces leakage power. Moreover, subthreshold operation, along with dynamic threshold techniques, is employed to achieve additional power reduction. The proposed cell is evaluated through HSPICE simulations using 32 nm carbon nanotube field-effect transistor (CNFET) technology. Monte Carlo analysis shows that the write margin (WM), read static noise margin (RSNM), and hold static noise margin (HSNM) are 139.9 mV, 65.4 mV, and 63.9 mV, respectively. The write and read access times are 228.2 ps and 209.8 ps, respectively. The maximum write power consumption is 3.8 nW, while the read and leakage power are 10.4 nW and 252.2 pW, respectively. The minimum operating voltage is 150 mV, with an RSNM of 26 mV. The proposed 10 T SRAM cell occupies an area of about 0.161 μm<sup>2</sup>.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"304 ","pages":"Article 112438"},"PeriodicalIF":3.1,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145871679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Effect of thermally-induced cracks on the mechanical and electrical behaviour of TGVs 热致裂纹对tgv力学和电学性能的影响

IF 3.1 4区工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronic Engineering

Pub Date : 2026-06-01 Epub Date: 2025-12-30 DOI: 10.1016/j.mee.2025.112441

Mugdha Sharma , Pradeep Dixit , Sanjeev Manhas

Through-glass vias (TGVs) are gaining importance in 2.5D/3D packaging due to their low electrical loss, dimensional stability, and panel-level manufacturability. However, the large mismatch in coefficient of thermal expansion (CTE) between copper(Cu) and glass induces significant thermo-mechanical stresses during temperature variations, leading to crack initiation, energy release, and electrical degradation. In this work, a coupled finite element method (FEM) and fracture mechanics framework is developed to analyze the reliability of Cu-filled TGVs. The study evaluates stress distribution, deformation, and current density in the presence of cracks positioned at different locations within the via and along the Cu–glass interface. The fracture driving force is quantified using the Energy Release Rate (ERR), with analytical formulations validated against FEM-based J-integral calculations. Results show that ERR scales linearly with via diameter and quadratically with temperature change magnitude, with peak values occurring when the crack length is approximately one-fourth of the via diameter. Substrate material strongly influences reliability, as fused silica produces the highest stresses and ERR, while ceramic glass gives better reliability. The introduction of polymer buffer layers significantly reduces stress in the TGV, demonstrating their effectiveness in mitigating mismatch-induced failures. Altogether, the combined FEM–ERR framework provides a unified basis for linking stress, fracture, and electrical degradation, and offers practical design guidelines for optimizing TGV-based interposers.

由于其低电损耗、尺寸稳定性和面板级可制造性，玻璃通孔（tgv）在2.5D/3D封装中越来越重要。然而，在温度变化过程中，铜（Cu）和玻璃之间的热膨胀系数（CTE）的大不匹配会引起显著的热机械应力，导致裂纹萌生、能量释放和电降解。本文建立了有限元法和断裂力学框架相结合的方法来分析充铜tgv的可靠性。该研究评估了在孔内和铜玻璃界面的不同位置存在裂纹时的应力分布、变形和电流密度。利用能量释放率（ERR）对裂缝驱动力进行量化，并根据基于有限元的j积分计算验证了分析公式。结果表明，ERR与通孔直径成线性关系，与温度变化幅度成二次关系，裂纹长度约为通孔直径的1 / 4时出现峰值；衬底材料强烈影响可靠性，熔融石英产生最高的应力和ERR，而陶瓷玻璃提供更好的可靠性。聚合物缓冲层的引入显著降低了TGV中的应力，证明了它们在减轻错配引起的故障方面的有效性。总之，结合FEM-ERR框架为连接应力、断裂和电气退化提供了统一的基础，并为优化基于tgv的中介器提供了实用的设计指南。

{"title":"Effect of thermally-induced cracks on the mechanical and electrical behaviour of TGVs","authors":"Mugdha Sharma , Pradeep Dixit , Sanjeev Manhas","doi":"10.1016/j.mee.2025.112441","DOIUrl":"10.1016/j.mee.2025.112441","url":null,"abstract":"<div><div>Through-glass vias (TGVs) are gaining importance in 2.5D/3D packaging due to their low electrical loss, dimensional stability, and panel-level manufacturability. However, the large mismatch in coefficient of thermal expansion (CTE) between copper(Cu) and glass induces significant thermo-mechanical stresses during temperature variations, leading to crack initiation, energy release, and electrical degradation. In this work, a coupled finite element method (FEM) and fracture mechanics framework is developed to analyze the reliability of Cu-filled TGVs. The study evaluates stress distribution, deformation, and current density in the presence of cracks positioned at different locations within the via and along the Cu–glass interface. The fracture driving force is quantified using the Energy Release Rate (ERR), with analytical formulations validated against FEM-based J-integral calculations. Results show that ERR scales linearly with via diameter and quadratically with temperature change magnitude, with peak values occurring when the crack length is approximately one-fourth of the via diameter. Substrate material strongly influences reliability, as fused silica produces the highest stresses and ERR, while ceramic glass gives better reliability. The introduction of polymer buffer layers significantly reduces stress in the TGV, demonstrating their effectiveness in mitigating mismatch-induced failures. Altogether, the combined FEM–ERR framework provides a unified basis for linking stress, fracture, and electrical degradation, and offers practical design guidelines for optimizing TGV-based interposers.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"304 ","pages":"Article 112441"},"PeriodicalIF":3.1,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145940571","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Variability in HfO2-based memristors under pulse operation 脉冲操作下hfo2基忆阻器的可变性

IF 3.1 4区工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronic Engineering

Pub Date : 2026-06-01 Epub Date: 2026-01-22 DOI: 10.1016/j.mee.2026.112445

D. Maldonado , C. Acal , H. Ortiz , F. Navas-Gomez , A. Cantudo , C. Wenger , E. Pérez , J.B. Roldán

We have studied device-to-device variability in TiN/Ti/HfO₂/TiN devices under pulse operation. We measured extensively memristive devices that are CMOS integrated with different pulse trains, changing the pulse width and amplitude for groups of more than one hundred devices. The statistical parameters of the measured current were extracted to better understand the device physics under the pulse operation regime. An analytical model to describe synaptic depression and potentiation behavior in the device conductance is introduced, it fits accurately the means of the current data for all the pulse trains under study. In addition, an explanation of the measurements is enlightened with kinetic Monte Carlo simulations that allow the study of resistive switching at the atomic level. Finally, the probability distribution functions of the measured currents in some of the pulses within the pulse series employed are analyzed to extract the probability distribution that works better. A proposal for the implementation of device-to-device variability in the Stanford models is introduced.

我们研究了脉冲操作下TiN/Ti/HfO2/TiN器件的器件间可变性。我们测量了广泛的记忆器件，这些器件集成了不同的脉冲序列，改变了一百多个器件组的脉冲宽度和幅度。提取了测量电流的统计参数，以便更好地了解器件在脉冲工作状态下的物理特性。介绍了一种描述装置电导中突触抑制和增强行为的解析模型，该模型准确地拟合了所研究的所有脉冲序列的当前数据均值。此外，动力学蒙特卡罗模拟对测量结果进行了解释，该模拟允许在原子水平上研究电阻开关。最后，对所采用的脉冲序列中某些脉冲中被测电流的概率分布函数进行了分析，以提取出效果较好的概率分布。介绍了在斯坦福模型中实现设备间可变性的建议。

{"title":"Variability in HfO2-based memristors under pulse operation","authors":"D. Maldonado , C. Acal , H. Ortiz , F. Navas-Gomez , A. Cantudo , C. Wenger , E. Pérez , J.B. Roldán","doi":"10.1016/j.mee.2026.112445","DOIUrl":"10.1016/j.mee.2026.112445","url":null,"abstract":"<div><div>We have studied device-to-device variability in TiN/Ti/HfO<sub>2</sub>/TiN devices under pulse operation. We measured extensively memristive devices that are CMOS integrated with different pulse trains, changing the pulse width and amplitude for groups of more than one hundred devices. The statistical parameters of the measured current were extracted to better understand the device physics under the pulse operation regime. An analytical model to describe synaptic depression and potentiation behavior in the device conductance is introduced, it fits accurately the means of the current data for all the pulse trains under study. In addition, an explanation of the measurements is enlightened with kinetic Monte Carlo simulations that allow the study of resistive switching at the atomic level. Finally, the probability distribution functions of the measured currents in some of the pulses within the pulse series employed are analyzed to extract the probability distribution that works better. A proposal for the implementation of device-to-device variability in the Stanford models is introduced.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"304 ","pages":"Article 112445"},"PeriodicalIF":3.1,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146078754","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An electromagnetic study of scalability of Si3N4 optical waveguides for 3D nanophotonic integration with CMOS electronics in AI era 人工智能时代CMOS电子器件三维纳米光子集成Si3N4光波导可扩展性的电磁研究

IF 3.1 4区工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronic Engineering

Pub Date : 2026-06-01 Epub Date: 2026-01-02 DOI: 10.1016/j.mee.2025.112440

Wenli Zhou , Rui (Ray) Yao , Sang Lam

We report computational electromagnetic (EM) investigation into the planar optical waveguide with the silicon nitride (Si₃N₄) core scaled down from 800 nm to 60 nm. The surrounding cladding of silicon dioxide (SiO₂) is at least 2 μm thick. With the CMOS-compatible Si₃N₄ optical waveguide constructed on a resistive silicon (Si) substrate, EM fields of the whole structure are computed by solving Maxwell's equations based on the finite element method (FEM). Electric field profiles of the fundamental mode are obtained at 900 nm wavelength (λ) which is shorter than the bandgap wavelength of Si and hence optical loss in the substrate. It is found that in scaling down the Si₃N₄ core to sub-wavelength thickness (i.e. less than (λ/n)), the evanescent electric field penetrates strongly through the SiO₂ under-cladding into the resistive substrate. The field penetration is even stronger for core thickness of 100 nm and 60 nm, which are equivalent to 0.22(λ/n) and 0.13(λ/n) respectively. Apart from using SiO₂ cladding of 4 μm or thicker, doubling the core width to increase the width-to-thickness ratio would provide alleviation. The results provide helpful guidelines about the Si₃N₄ thickness, width and spatial separation, in the design and fabrication of nanophotonic devices and circuits for potential 3D integration with CMOS electronics built on the Si substrate.

我们报道了对平面光波导的计算电磁（EM）研究，其中氮化硅（Si3N4）核心从800 nm缩小到60 nm。表面的SiO2包层厚度不小于2 μm。将cmos兼容的Si3N4光波导构建在电阻硅（Si）衬底上，利用基于有限元法求解Maxwell方程计算了整个结构的电磁场。在900 nm波长（λ）处得到基模的电场分布，该波长比硅的带隙波长短，因此在衬底中存在光学损耗。研究发现，当Si3N4芯缩小到亚波长厚度（即小于（λ/n））时，瞬变电场通过SiO2包层强烈渗透到电阻基板中。当芯厚为100 nm和60 nm时，电场穿透力更强，分别相当于0.22（λ/n）和0.13（λ/n）。除了使用4 μm或更厚的SiO2包层外，将芯宽增加一倍以增加宽厚比也可以起到缓解作用。研究结果为设计和制造纳米光子器件和电路提供了有关Si3N4厚度、宽度和空间分离的有用指导，这些器件和电路可能与基于Si衬底的CMOS电子器件进行3D集成。

{"title":"An electromagnetic study of scalability of Si3N4 optical waveguides for 3D nanophotonic integration with CMOS electronics in AI era","authors":"Wenli Zhou , Rui (Ray) Yao , Sang Lam","doi":"10.1016/j.mee.2025.112440","DOIUrl":"10.1016/j.mee.2025.112440","url":null,"abstract":"<div><div>We report computational electromagnetic (EM) investigation into the planar optical waveguide with the silicon nitride (Si<sub>3</sub>N<sub>4</sub>) core scaled down from 800 nm to 60 nm. The surrounding cladding of silicon dioxide (SiO<sub>2</sub>) is at least 2 μm thick. With the CMOS-compatible Si<sub>3</sub>N<sub>4</sub> optical waveguide constructed on a resistive silicon (Si) substrate, EM fields of the whole structure are computed by solving Maxwell's equations based on the finite element method (FEM). Electric field profiles of the fundamental mode are obtained at 900 nm wavelength (λ) which is shorter than the bandgap wavelength of Si and hence optical loss in the substrate. It is found that in scaling down the Si<sub>3</sub>N<sub>4</sub> core to sub-wavelength thickness (i.e. less than (λ/<em>n</em>)), the evanescent electric field penetrates strongly through the SiO<sub>2</sub> under-cladding into the resistive substrate. The field penetration is even stronger for core thickness of 100 nm and 60 nm, which are equivalent to 0.22(λ/<em>n</em>) and 0.13(λ/<em>n</em>) respectively. Apart from using SiO<sub>2</sub> cladding of 4 μm or thicker, doubling the core width to increase the width-to-thickness ratio would provide alleviation. The results provide helpful guidelines about the Si<sub>3</sub>N<sub>4</sub> thickness, width and spatial separation, in the design and fabrication of nanophotonic devices and circuits for potential 3D integration with CMOS electronics built on the Si substrate.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"304 ","pages":"Article 112440"},"PeriodicalIF":3.1,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146078665","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Research on evaluation method of data retention capability of STT-MRAM chips STT-MRAM芯片数据保留能力评估方法研究

IF 3.1 4区工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronic Engineering

Pub Date : 2026-03-01 Epub Date: 2025-11-25 DOI: 10.1016/j.mee.2025.112427

Jiejie Sun , Meining Ji , Hongguang Shen , Chuanpeng Jiang , Chao Wang , Meng Zhang , Kaihua Cao , Bi Wang , Haibo Ye

Data retention time, a crucial reliability parameter in spin-transfer torque magnetic random access memory (STT-MRAM), characterizes the capability to maintain stable data storage time. Methods for evaluating data retention time often face the issues of excessive test time and limited precision. This study investigates the data retention capability of STT-MRAM chips by using high-temperature acceleration and magnetic-field acceleration methods, which significantly enhance both testing efficiency and accuracy. The two acceleration methods show high consistency in predicting E_Bmeff and Δ_eff, with a relative deviation of only 10 % at −25 °C. Furthermore, the observed dependence of E_Beff on the magnetic field aligns well with theoretical predictions derived from the domain wall model. Experimental results show that STT-MRAM chips can achieve a data retention time exceeding 20 years at 105 °C, fulfilling the stringent reliability criteria required for industrial-grade memory applications. These findings provide critical experimental verification and technical insights to support the integration of STT-MRAM into next-generation memory architectures.

数据保持时间是自旋传递转矩磁随机存储器（STT-MRAM）可靠性的关键参数，它表征了数据保持稳定存储时间的能力。评估数据保留时间的方法经常面临测试时间过长和精度有限的问题。本研究采用高温加速和磁场加速两种方法对STT-MRAM芯片的数据保留能力进行了研究，显著提高了测试效率和准确性。两种加速方法在预测EBmeff和Δeff时具有较高的一致性，在- 25°C时相对偏差仅为10%。此外，观测到的EBeff对磁场的依赖性与从畴壁模型得出的理论预测很好地吻合。实验结果表明，STT-MRAM芯片可以在105°C下实现超过20年的数据保留时间，满足工业级存储器应用所需的严格可靠性标准。这些发现为支持STT-MRAM集成到下一代存储器架构中提供了关键的实验验证和技术见解。

{"title":"Research on evaluation method of data retention capability of STT-MRAM chips","authors":"Jiejie Sun , Meining Ji , Hongguang Shen , Chuanpeng Jiang , Chao Wang , Meng Zhang , Kaihua Cao , Bi Wang , Haibo Ye","doi":"10.1016/j.mee.2025.112427","DOIUrl":"10.1016/j.mee.2025.112427","url":null,"abstract":"<div><div>Data retention time, a crucial reliability parameter in spin-transfer torque magnetic random access memory (STT-MRAM), characterizes the capability to maintain stable data storage time. Methods for evaluating data retention time often face the issues of excessive test time and limited precision. This study investigates the data retention capability of STT-MRAM chips by using high-temperature acceleration and magnetic-field acceleration methods, which significantly enhance both testing efficiency and accuracy. The two acceleration methods show high consistency in predicting <em>E</em><sub>Bmeff</sub> and <em>Δ</em><sub>eff</sub>, with a relative deviation of only 10 % at −25 °C. Furthermore, the observed dependence of <em>E</em><sub>Beff</sub> on the magnetic field aligns well with theoretical predictions derived from the domain wall model. Experimental results show that STT-MRAM chips can achieve a data retention time exceeding 20 years at 105 °C, fulfilling the stringent reliability criteria required for industrial-grade memory applications. These findings provide critical experimental verification and technical insights to support the integration of STT-MRAM into next-generation memory architectures.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"303 ","pages":"Article 112427"},"PeriodicalIF":3.1,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145623074","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Graphene nanoribbon interconnects for RF sensing: Modeling and performance analysis using ring oscillators 用于射频传感的石墨烯纳米带互连：环形振荡器的建模和性能分析

IF 3.1 4区工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronic Engineering

Pub Date : 2026-03-01 Epub Date: 2026-01-03 DOI: 10.1016/j.mee.2025.112442

Sandip Bhattacharya , Tan Cher Ming , Subhajit Das , Abir Chattopadhyay

In the proposed work, our SPICE-compatible compact RF model of multi-layer graphene nanoribbon (MLGNR) interconnect is interfaced with 3-stage ring oscillator to validate the circuit performance of MLGNR interconnect in on-chip RF sensing applications. The 16 nm CMOS process technology PTM model has been paired with 16 nm MLGNR interconnect considering the ITRS-13 to design, validate and analyze power consumption, propagation delay, and noise characteristics of the basic ring oscillator in high-frequency generation for RF sensing applications. The comparative performance with conventional copper interconnect and side-contact MLGNR interconnect is analyzed. Our study revealed that the use of side-contact GNR (SC-GNR) with a mean free path (MFP) of near 1000 nm outperforms other interconnect materials such as Cu, SC-GNR (MFP = 300 nm), and SC-GNR (MFP = 419 nm). Specifically, SC-GNR with MFP of 1000 nm can achieve a max frequency of 4.8 GHz, making it highly suitable for high-speed data processing while consuming ∼2–3 times less power and exhibiting ∼2.5–3.5 times less delay compared to alternative interconnects in RF sensing applications.

在我们提出的工作中，我们的spice兼容多层石墨烯纳米带（MLGNR）互连的紧凑型射频模型与3级环形振荡器接口，以验证MLGNR互连在片上射频传感应用中的电路性能。基于ITRS-13，将16纳米CMOS工艺技术PTM模型与16纳米MLGNR互连相结合，设计、验证和分析射频传感应用中高频产生的基本环振荡器的功耗、传播延迟和噪声特性。分析了其与传统铜互连和边接触MLGNR互连的性能对比。我们的研究表明，使用平均自由程（MFP）接近1000 nm的侧接触GNR （SC-GNR）优于其他互连材料，如Cu， SC-GNR （MFP = 300 nm）和SC-GNR （MFP = 419 nm）。具体而言，MFP为1000 nm的SC-GNR可以实现4.8 GHz的最大频率，使其非常适合高速数据处理，同时与RF传感应用中的替代互连相比，功耗降低~ 2-3倍，延迟降低~ 2.5-3.5倍。

{"title":"Graphene nanoribbon interconnects for RF sensing: Modeling and performance analysis using ring oscillators","authors":"Sandip Bhattacharya , Tan Cher Ming , Subhajit Das , Abir Chattopadhyay","doi":"10.1016/j.mee.2025.112442","DOIUrl":"10.1016/j.mee.2025.112442","url":null,"abstract":"<div><div>In the proposed work, our SPICE-compatible compact RF model of multi-layer graphene nanoribbon (MLGNR) interconnect is interfaced with 3-stage ring oscillator to validate the circuit performance of MLGNR interconnect in on-chip RF sensing applications. The 16 nm CMOS process technology PTM model has been paired with 16 nm MLGNR interconnect considering the ITRS-13 to design, validate and analyze power consumption, propagation delay, and noise characteristics of the basic ring oscillator in high-frequency generation for RF sensing applications. The comparative performance with conventional copper interconnect and side-contact MLGNR interconnect is analyzed. Our study revealed that the use of side-contact GNR (SC-GNR) with a mean free path (MFP) of near 1000 nm outperforms other interconnect materials such as Cu, SC-GNR (MFP = 300 nm), and SC-GNR (MFP = 419 nm). Specifically, SC-GNR with MFP of 1000 nm can achieve a max frequency of 4.8 GHz, making it highly suitable for high-speed data processing while consuming ∼2–3 times less power and exhibiting ∼2.5–3.5 times less delay compared to alternative interconnects in RF sensing applications.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"303 ","pages":"Article 112442"},"PeriodicalIF":3.1,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145925214","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Comprehensive statistical analysis of random telegraph noise: Impact of gate voltage, temperature, and Bias time 随机电报噪声的综合统计分析：栅极电压、温度和偏置时间的影响

IF 3.1 4区工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronic Engineering

Pub Date : 2026-03-01 Epub Date: 2025-12-13 DOI: 10.1016/j.mee.2025.112437

J. Martin-Martinez , N. Baghban-Bousari , R. Castro-Lopez , D. Eric , E. Roca , R. Rodriguez , M. Porti , F.V. Fernandez , M. Nafria

This work presents a statistical analysis of Random Telegraph Noise (RTN) in nanoscale MOSFETs, from more than 13,000 traces measured under varying voltages, temperatures, and bias times on an array-based characterization chip. Using the Weighted Time Lag Plot (WTLP), we extracted the average number of detectable traps and the associated current step amplitudes. Results show that the average number of detectable traps increases with voltage and temperature but decreases after some bias time due to a transient trap population. The average current step amplitude grows with voltage and shows negligible dependence on temperature. These findings support improved RTN modeling and are relevant for both reliability analysis and cryptographic applications.

这项工作提出了纳米级mosfet中随机电报噪声（RTN）的统计分析，来自基于阵列的表征芯片上在不同电压，温度和偏置时间下测量的13,000多条走线。利用加权时滞图（WTLP），我们提取了可探测陷阱的平均数量和相关的电流阶跃幅值。结果表明，可探测陷阱的平均数量随着电压和温度的增加而增加，但由于瞬态陷阱数量在一定偏置时间后减少。平均电流阶跃幅值随电压增长，对温度的依赖性可以忽略不计。这些发现支持改进的RTN建模，并且与可靠性分析和密码学应用相关。

引用次数: 0

Asynchronous real-time learning in Spiking Neural Network using 3-terminal Resistance Random Access Memory 基于3端电阻随机存取存储器的脉冲神经网络异步实时学习

IF 3.1 4区工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronic Engineering

Pub Date : 2026-03-01 Epub Date: 2025-11-22 DOI: 10.1016/j.mee.2025.112429

Harshvardhan Singh , Nirmal Solanki , Jaskirat Singh Maskeen , Shalu Saini , Madhav Pathak , Sandip Lashkare

Spiking Neural Networks (SNNs) inspired by the human brain are promising alternative to solve real-life complex problems, such as pattern recognition at low energy consumption. A key approach to implementing SNNs involves using a Resistance Random Access Memory (RRAM) crossbar array to simulate synaptic weights, which can have multi-step resistance states suitable for processing analog signals. However, a major hurdle with traditional 2-terminal RRAMs is the “read–write dilemma”: the low voltage needed for a non-destructive read operation conflicts with the high voltage required for a write operation, making simultaneous, real-time learning challenging. Current solutions to this problem, such as time or frequency division multiplexing and separate read/write arrays, increase the circuit’s complexity, size, or operation time. This paper proposes a novel solution using a recently developed 3-terminal (3T)

{Pr}_{0.7} {Ca}_{0.3} {MnO}_{3}

(PCMO) RRAM. By using two terminals for writing and a third, dedicated decoupled terminal for reading, this architecture allows for simultaneous and asynchronous read and write operations. This approach resolves the read–write conflict inherent in 2-terminal designs, enabling real-time learning in SNNs without significant increase in circuit overhead and learning time.

受人脑启发的脉冲神经网络（SNNs）有望解决现实生活中的复杂问题，如低能耗模式识别。实现snn的一个关键方法是使用电阻随机存取存储器（RRAM）交叉棒阵列来模拟突触权重，它可以具有适合处理模拟信号的多步电阻状态。然而，传统的2端rram的一个主要障碍是“读写困境”：非破坏性读取操作所需的低电压与写入操作所需的高电压相冲突，这使得同步、实时学习变得困难。目前解决这个问题的方案，如时分或频分复用和单独的读/写阵列，增加了电路的复杂性、尺寸或操作时间。本文提出了一种新的解决方案，使用最新开发的3端（3T） Pr0.7Ca0.3MnO3 (PCMO) RRAM。通过使用两个终端进行写入，使用第三个专用的解耦终端进行读取，这种体系结构允许同时和异步读写操作。这种方法解决了双端设计中固有的读写冲突，在不显著增加电路开销和学习时间的情况下实现了snn的实时学习。

{"title":"Asynchronous real-time learning in Spiking Neural Network using 3-terminal Resistance Random Access Memory","authors":"Harshvardhan Singh , Nirmal Solanki , Jaskirat Singh Maskeen , Shalu Saini , Madhav Pathak , Sandip Lashkare","doi":"10.1016/j.mee.2025.112429","DOIUrl":"10.1016/j.mee.2025.112429","url":null,"abstract":"<div><div>Spiking Neural Networks (SNNs) inspired by the human brain are promising alternative to solve real-life complex problems, such as pattern recognition at low energy consumption. A key approach to implementing SNNs involves using a Resistance Random Access Memory (RRAM) crossbar array to simulate synaptic weights, which can have multi-step resistance states suitable for processing analog signals. However, a major hurdle with traditional 2-terminal RRAMs is the “read–write dilemma”: the low voltage needed for a non-destructive read operation conflicts with the high voltage required for a write operation, making simultaneous, real-time learning challenging. Current solutions to this problem, such as time or frequency division multiplexing and separate read/write arrays, increase the circuit’s complexity, size, or operation time. This paper proposes a novel solution using a recently developed 3-terminal (3T) <span><math><mrow><msub><mrow><mtext>Pr</mtext></mrow><mrow><mn>0</mn><mo>.</mo><mn>7</mn></mrow></msub><msub><mrow><mtext>Ca</mtext></mrow><mrow><mn>0</mn><mo>.</mo><mn>3</mn></mrow></msub><msub><mrow><mtext>MnO</mtext></mrow><mrow><mn>3</mn></mrow></msub></mrow></math></span> (PCMO) RRAM. By using two terminals for writing and a third, dedicated decoupled terminal for reading, this architecture allows for simultaneous and asynchronous read and write operations. This approach resolves the read–write conflict inherent in 2-terminal designs, enabling real-time learning in SNNs without significant increase in circuit overhead and learning time.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"303 ","pages":"Article 112429"},"PeriodicalIF":3.1,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145622910","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0