Pub Date : 2026-01-22DOI: 10.1016/j.mee.2026.112445
D. Maldonado , C. Acal , H. Ortiz , F. Navas-Gomez , A. Cantudo , C. Wenger , E. Pérez , J.B. Roldán
We have studied device-to-device variability in TiN/Ti/HfO2/TiN devices under pulse operation. We measured extensively memristive devices that are CMOS integrated with different pulse trains, changing the pulse width and amplitude for groups of more than one hundred devices. The statistical parameters of the measured current were extracted to better understand the device physics under the pulse operation regime. An analytical model to describe synaptic depression and potentiation behavior in the device conductance is introduced, it fits accurately the means of the current data for all the pulse trains under study. In addition, an explanation of the measurements is enlightened with kinetic Monte Carlo simulations that allow the study of resistive switching at the atomic level. Finally, the probability distribution functions of the measured currents in some of the pulses within the pulse series employed are analyzed to extract the probability distribution that works better. A proposal for the implementation of device-to-device variability in the Stanford models is introduced.
{"title":"Variability in HfO2-based memristors under pulse operation","authors":"D. Maldonado , C. Acal , H. Ortiz , F. Navas-Gomez , A. Cantudo , C. Wenger , E. Pérez , J.B. Roldán","doi":"10.1016/j.mee.2026.112445","DOIUrl":"10.1016/j.mee.2026.112445","url":null,"abstract":"<div><div>We have studied device-to-device variability in TiN/Ti/HfO<sub>2</sub>/TiN devices under pulse operation. We measured extensively memristive devices that are CMOS integrated with different pulse trains, changing the pulse width and amplitude for groups of more than one hundred devices. The statistical parameters of the measured current were extracted to better understand the device physics under the pulse operation regime. An analytical model to describe synaptic depression and potentiation behavior in the device conductance is introduced, it fits accurately the means of the current data for all the pulse trains under study. In addition, an explanation of the measurements is enlightened with kinetic Monte Carlo simulations that allow the study of resistive switching at the atomic level. Finally, the probability distribution functions of the measured currents in some of the pulses within the pulse series employed are analyzed to extract the probability distribution that works better. A proposal for the implementation of device-to-device variability in the Stanford models is introduced.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"304 ","pages":"Article 112445"},"PeriodicalIF":3.1,"publicationDate":"2026-01-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146078754","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-01-21DOI: 10.1016/j.mee.2026.112452
Enjing Cai , Limin Zhou , Qiang Chen , David Wei Zhang , Qingqing Sun , Hao Zhu
As CMOS technology scales to the 28 nm node and beyond, systematic yield limiters such as layout-dependent effects (LDE) and back-end-of-line (BEOL) weak patterns induced by routing congestion become increasingly pronounced. This creates a significant “SRAM-to-Product” gap, where conventional static random-access memory (SRAM)-based process monitoring inadequately reflects actual product performance. Moreover, the inherent time-consuming and resource-intensive nature of failure analysis (FA) for product-like monitors, primarily due to their dependency on complex electronic design automation (EDA)-based diagnostics, constitutes a severe FA bottleneck. In this paper, we present a novel product qualification vehicle (PQV), implemented on a 28 nm high-k/metal gate (HKMG) platform, that effectively bridges this critical gap. The PQV incorporates dedicated arrays of bit-cells constructed from standard logic gates, strategically designed to authentically replicate product-level LDE and BEOL stressors through a realistic place & route (P&R) flow. Crucially, it features an EDA-less diagnostic engine that provides direct physical coordinates of failing bits, thereby streamlining fault isolation by completely eliminating the need for conventional EDA tools. Silicon validation demonstrates that the PQV successfully captures critical LDE-induced functional failures and BEOL via-open defects systematically missed by conventional SRAMs. This methodology accelerates the fault-to-physical root-cause diagnosis cycle by over twelve times, facilitating rapid process learning and substantially reducing time-to-market.
{"title":"A product qualification vehicle (PQV) for accelerated yield learning and efficient fault isolation in 28 nm HKMG technologies by capturing LDE and BEOL weak patterns","authors":"Enjing Cai , Limin Zhou , Qiang Chen , David Wei Zhang , Qingqing Sun , Hao Zhu","doi":"10.1016/j.mee.2026.112452","DOIUrl":"10.1016/j.mee.2026.112452","url":null,"abstract":"<div><div>As CMOS technology scales to the 28 nm node and beyond, systematic yield limiters such as layout-dependent effects (LDE) and back-end-of-line (BEOL) weak patterns induced by routing congestion become increasingly pronounced. This creates a significant “SRAM-to-Product” gap, where conventional static random-access memory (SRAM)-based process monitoring inadequately reflects actual product performance. Moreover, the inherent time-consuming and resource-intensive nature of failure analysis (FA) for product-like monitors, primarily due to their dependency on complex electronic design automation (EDA)-based diagnostics, constitutes a severe FA bottleneck. In this paper, we present a novel product qualification vehicle (PQV), implemented on a 28 nm high-k/metal gate (HKMG) platform, that effectively bridges this critical gap. The PQV incorporates dedicated arrays of bit-cells constructed from standard logic gates, strategically designed to authentically replicate product-level LDE and BEOL stressors through a realistic place & route (P&R) flow. Crucially, it features an EDA-less diagnostic engine that provides direct physical coordinates of failing bits, thereby streamlining fault isolation by completely eliminating the need for conventional EDA tools. Silicon validation demonstrates that the PQV successfully captures critical LDE-induced functional failures and BEOL via-open defects systematically missed by conventional SRAMs. This methodology accelerates the fault-to-physical root-cause diagnosis cycle by over twelve times, facilitating rapid process learning and substantially reducing time-to-market.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"304 ","pages":"Article 112452"},"PeriodicalIF":3.1,"publicationDate":"2026-01-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146090391","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-01-12DOI: 10.1016/j.mee.2025.112444
Maleeha Abdul Azeez, Dhanaraj K.J.
Spiking Neural Networks (SNNs) are a class of Artificial Neural Networks (ANNs) that process information encoded in spike trains. Hardware implementations of spiking neurons, the building blocks of SNNs, reveal that SNNs can be realized as low-power and high-density neural networks. In this work, a spiking neuron design realized using a CMOS-based monostable multivibrator circuit is proposed. Performance comparisons with similar spiking neuron designs show that the proposed neuron exhibits high robustness to hardware variations in addition to its low power, low area, and low latency characteristics. The ability to operate over a wide range of spike rates enables deployment of the neuron in a wide variety of applications. SNNs using rate encoding and TTFS (Time-To-First-Spike) encoding designed with the proposed neuron exhibit better performance results in comparison with those realized using other similar designs in the simulation studies. The possibility of using the neuron for large-scale SNNs is also explored. Post-layout simulations of the neuron and two SNNs built with the neuron also show high robustness, conforming with the corresponding results from the pre-layout simulations. With an active footprint area of and energy per spike as low as 100 fJ, the monostable multivibrator-based neuron proves to be a simple, compact, energy-efficient and variation-tolerant spiking neuron, which is a good candidate for building diverse SNNs.
{"title":"Variation-robust CMOS monostable multivibrator-based spiking neuron and spiking neural networks","authors":"Maleeha Abdul Azeez, Dhanaraj K.J.","doi":"10.1016/j.mee.2025.112444","DOIUrl":"10.1016/j.mee.2025.112444","url":null,"abstract":"<div><div>Spiking Neural Networks (SNNs) are a class of Artificial Neural Networks (ANNs) that process information encoded in spike trains. Hardware implementations of spiking neurons, the building blocks of SNNs, reveal that SNNs can be realized as low-power and high-density neural networks. In this work, a spiking neuron design realized using a CMOS-based monostable multivibrator circuit is proposed. Performance comparisons with similar spiking neuron designs show that the proposed neuron exhibits high robustness to hardware variations in addition to its low power, low area, and low latency characteristics. The ability to operate over a wide range of spike rates enables deployment of the neuron in a wide variety of applications. SNNs using rate encoding and TTFS (Time-To-First-Spike) encoding designed with the proposed neuron exhibit better performance results in comparison with those realized using other similar designs in the simulation studies. The possibility of using the neuron for large-scale SNNs is also explored. Post-layout simulations of the neuron and two SNNs built with the neuron also show high robustness, conforming with the corresponding results from the pre-layout simulations. With an active footprint area of <span><math><mrow><mn>33</mn><mspace></mspace><mi>μ</mi><msup><mrow><mi>m</mi></mrow><mrow><mn>2</mn></mrow></msup></mrow></math></span> and energy per spike as low as 100 fJ, the monostable multivibrator-based neuron proves to be a simple, compact, energy-efficient and variation-tolerant spiking neuron, which is a good candidate for building diverse SNNs.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"304 ","pages":"Article 112444"},"PeriodicalIF":3.1,"publicationDate":"2026-01-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145978972","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-01-03DOI: 10.1016/j.mee.2025.112442
Sandip Bhattacharya , Tan Cher Ming , Subhajit Das , Abir Chattopadhyay
In the proposed work, our SPICE-compatible compact RF model of multi-layer graphene nanoribbon (MLGNR) interconnect is interfaced with 3-stage ring oscillator to validate the circuit performance of MLGNR interconnect in on-chip RF sensing applications. The 16 nm CMOS process technology PTM model has been paired with 16 nm MLGNR interconnect considering the ITRS-13 to design, validate and analyze power consumption, propagation delay, and noise characteristics of the basic ring oscillator in high-frequency generation for RF sensing applications. The comparative performance with conventional copper interconnect and side-contact MLGNR interconnect is analyzed. Our study revealed that the use of side-contact GNR (SC-GNR) with a mean free path (MFP) of near 1000 nm outperforms other interconnect materials such as Cu, SC-GNR (MFP = 300 nm), and SC-GNR (MFP = 419 nm). Specifically, SC-GNR with MFP of 1000 nm can achieve a max frequency of 4.8 GHz, making it highly suitable for high-speed data processing while consuming ∼2–3 times less power and exhibiting ∼2.5–3.5 times less delay compared to alternative interconnects in RF sensing applications.
{"title":"Graphene nanoribbon interconnects for RF sensing: Modeling and performance analysis using ring oscillators","authors":"Sandip Bhattacharya , Tan Cher Ming , Subhajit Das , Abir Chattopadhyay","doi":"10.1016/j.mee.2025.112442","DOIUrl":"10.1016/j.mee.2025.112442","url":null,"abstract":"<div><div>In the proposed work, our SPICE-compatible compact RF model of multi-layer graphene nanoribbon (MLGNR) interconnect is interfaced with 3-stage ring oscillator to validate the circuit performance of MLGNR interconnect in on-chip RF sensing applications. The 16 nm CMOS process technology PTM model has been paired with 16 nm MLGNR interconnect considering the ITRS-13 to design, validate and analyze power consumption, propagation delay, and noise characteristics of the basic ring oscillator in high-frequency generation for RF sensing applications. The comparative performance with conventional copper interconnect and side-contact MLGNR interconnect is analyzed. Our study revealed that the use of side-contact GNR (SC-GNR) with a mean free path (MFP) of near 1000 nm outperforms other interconnect materials such as Cu, SC-GNR (MFP = 300 nm), and SC-GNR (MFP = 419 nm). Specifically, SC-GNR with MFP of 1000 nm can achieve a max frequency of 4.8 GHz, making it highly suitable for high-speed data processing while consuming ∼2–3 times less power and exhibiting ∼2.5–3.5 times less delay compared to alternative interconnects in RF sensing applications.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"303 ","pages":"Article 112442"},"PeriodicalIF":3.1,"publicationDate":"2026-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145925214","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-01-02DOI: 10.1016/j.mee.2025.112440
Wenli Zhou , Rui (Ray) Yao , Sang Lam
We report computational electromagnetic (EM) investigation into the planar optical waveguide with the silicon nitride (Si3N4) core scaled down from 800 nm to 60 nm. The surrounding cladding of silicon dioxide (SiO2) is at least 2 μm thick. With the CMOS-compatible Si3N4 optical waveguide constructed on a resistive silicon (Si) substrate, EM fields of the whole structure are computed by solving Maxwell's equations based on the finite element method (FEM). Electric field profiles of the fundamental mode are obtained at 900 nm wavelength (λ) which is shorter than the bandgap wavelength of Si and hence optical loss in the substrate. It is found that in scaling down the Si3N4 core to sub-wavelength thickness (i.e. less than (λ/n)), the evanescent electric field penetrates strongly through the SiO2 under-cladding into the resistive substrate. The field penetration is even stronger for core thickness of 100 nm and 60 nm, which are equivalent to 0.22(λ/n) and 0.13(λ/n) respectively. Apart from using SiO2 cladding of 4 μm or thicker, doubling the core width to increase the width-to-thickness ratio would provide alleviation. The results provide helpful guidelines about the Si3N4 thickness, width and spatial separation, in the design and fabrication of nanophotonic devices and circuits for potential 3D integration with CMOS electronics built on the Si substrate.
{"title":"An electromagnetic study of scalability of Si3N4 optical waveguides for 3D nanophotonic integration with CMOS electronics in AI era","authors":"Wenli Zhou , Rui (Ray) Yao , Sang Lam","doi":"10.1016/j.mee.2025.112440","DOIUrl":"10.1016/j.mee.2025.112440","url":null,"abstract":"<div><div>We report computational electromagnetic (EM) investigation into the planar optical waveguide with the silicon nitride (Si<sub>3</sub>N<sub>4</sub>) core scaled down from 800 nm to 60 nm. The surrounding cladding of silicon dioxide (SiO<sub>2</sub>) is at least 2 μm thick. With the CMOS-compatible Si<sub>3</sub>N<sub>4</sub> optical waveguide constructed on a resistive silicon (Si) substrate, EM fields of the whole structure are computed by solving Maxwell's equations based on the finite element method (FEM). Electric field profiles of the fundamental mode are obtained at 900 nm wavelength (λ) which is shorter than the bandgap wavelength of Si and hence optical loss in the substrate. It is found that in scaling down the Si<sub>3</sub>N<sub>4</sub> core to sub-wavelength thickness (i.e. less than (λ/<em>n</em>)), the evanescent electric field penetrates strongly through the SiO<sub>2</sub> under-cladding into the resistive substrate. The field penetration is even stronger for core thickness of 100 nm and 60 nm, which are equivalent to 0.22(λ/<em>n</em>) and 0.13(λ/<em>n</em>) respectively. Apart from using SiO<sub>2</sub> cladding of 4 μm or thicker, doubling the core width to increase the width-to-thickness ratio would provide alleviation. The results provide helpful guidelines about the Si<sub>3</sub>N<sub>4</sub> thickness, width and spatial separation, in the design and fabrication of nanophotonic devices and circuits for potential 3D integration with CMOS electronics built on the Si substrate.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"304 ","pages":"Article 112440"},"PeriodicalIF":3.1,"publicationDate":"2026-01-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146078665","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-01-01DOI: 10.1016/j.mee.2025.112438
Mohammadhasan jali , S. Mohammadali Zanjani , Mehdi Dolatshahi , Behrang Barekatain
This paper presents a novel 10 T static random-access memory (SRAM) cell designed for low-power, high-speed, and half-selected disturbance-free applications, featuring a differential write operation and a separated single-ended read operation. To reduce power consumption and enhance write stability, one of the back-to-back inverters is dynamically based on bit line value, removed from the circuit during the write phase, without the need for auxiliary circuitry. This functionality is implemented using stacked transistors in a single inverter, which also reduces leakage power. Moreover, subthreshold operation, along with dynamic threshold techniques, is employed to achieve additional power reduction. The proposed cell is evaluated through HSPICE simulations using 32 nm carbon nanotube field-effect transistor (CNFET) technology. Monte Carlo analysis shows that the write margin (WM), read static noise margin (RSNM), and hold static noise margin (HSNM) are 139.9 mV, 65.4 mV, and 63.9 mV, respectively. The write and read access times are 228.2 ps and 209.8 ps, respectively. The maximum write power consumption is 3.8 nW, while the read and leakage power are 10.4 nW and 252.2 pW, respectively. The minimum operating voltage is 150 mV, with an RSNM of 26 mV. The proposed 10 T SRAM cell occupies an area of about 0.161 μm2.
{"title":"A new subthreshold half-select free SRAM with dynamic feedback cut-off for low-power and high speed applications","authors":"Mohammadhasan jali , S. Mohammadali Zanjani , Mehdi Dolatshahi , Behrang Barekatain","doi":"10.1016/j.mee.2025.112438","DOIUrl":"10.1016/j.mee.2025.112438","url":null,"abstract":"<div><div>This paper presents a novel 10 T static random-access memory (SRAM) cell designed for low-power, high-speed, and half-selected disturbance-free applications, featuring a differential write operation and a separated single-ended read operation. To reduce power consumption and enhance write stability, one of the back-to-back inverters is dynamically based on bit line value, removed from the circuit during the write phase, without the need for auxiliary circuitry. This functionality is implemented using stacked transistors in a single inverter, which also reduces leakage power. Moreover, subthreshold operation, along with dynamic threshold techniques, is employed to achieve additional power reduction. The proposed cell is evaluated through HSPICE simulations using 32 nm carbon nanotube field-effect transistor (CNFET) technology. Monte Carlo analysis shows that the write margin (WM), read static noise margin (RSNM), and hold static noise margin (HSNM) are 139.9 mV, 65.4 mV, and 63.9 mV, respectively. The write and read access times are 228.2 ps and 209.8 ps, respectively. The maximum write power consumption is 3.8 nW, while the read and leakage power are 10.4 nW and 252.2 pW, respectively. The minimum operating voltage is 150 mV, with an RSNM of 26 mV. The proposed 10 T SRAM cell occupies an area of about 0.161 μm<sup>2</sup>.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"304 ","pages":"Article 112438"},"PeriodicalIF":3.1,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145871679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-31DOI: 10.1016/j.mee.2025.112439
Surya Elangovan , Stone Cheng , Edward Yi Chang , Tejender Singh Rawat , Yi-Kai Hsiao , Chang-Ching Tu , Hao-Chung Kuo
A cascode gallium nitride (GaN) switch integrating two paralleled GaN depletion-mode metal-insulator-semiconductor (MIS) high-electron-mobility transistors (HEMT) and a silicon MOSFET (Si-MOSFET) are presented. Each GaN chip is wire-bonded into a multi-chip power module to scale up the power rating. An optimized symmetric configuration and wire bonding of an integral package are used in the novel cascode switch. The developed GaN cascode switch was verified for validity through both static and dynamic characterizations in an optimized package. Static characterization reveals a significant reduction in RDS-ON from 282 mΩ (single MIS-HEMT) to 146 mΩ (dual-GaN cascode) with a threshold voltage shift to 4.2 V, confirming safe and reliable enhancement-mode operation. Dynamic switching performance, evaluated using double-pulse testing, demonstrates that the dual-GaN configuration maintains fast turn-on/off times with minimal increase relative to a single-GaN cascode. Voltage- and current-dependent measurements indicate a moderate increase in dynamic RDS-ON due to charge trapping and hot carrier injection, which stabilizes at higher voltages. These results highlight the feasibility of paralleling GaN HEMTs in a cascode configuration to enhance performance, reliability, and scalability in high-power applications.
{"title":"Design and characterization of 2-GaN MIS-HEMT integrated cascode power module","authors":"Surya Elangovan , Stone Cheng , Edward Yi Chang , Tejender Singh Rawat , Yi-Kai Hsiao , Chang-Ching Tu , Hao-Chung Kuo","doi":"10.1016/j.mee.2025.112439","DOIUrl":"10.1016/j.mee.2025.112439","url":null,"abstract":"<div><div>A cascode gallium nitride (GaN) switch integrating two paralleled GaN depletion-mode metal-insulator-semiconductor (MIS) high-electron-mobility transistors (HEMT) and a silicon MOSFET (Si-MOSFET) are presented. Each GaN chip is wire-bonded into a multi-chip power module to scale up the power rating. An optimized symmetric configuration and wire bonding of an integral package are used in the novel cascode switch. The developed GaN cascode switch was verified for validity through both static and dynamic characterizations in an optimized package. Static characterization reveals a significant reduction in RDS-ON from 282 mΩ (single MIS-HEMT) to 146 mΩ (dual-GaN cascode) with a threshold voltage shift to 4.2 V, confirming safe and reliable enhancement-mode operation. Dynamic switching performance, evaluated using double-pulse testing, demonstrates that the dual-GaN configuration maintains fast turn-on/off times with minimal increase relative to a single-GaN cascode. Voltage- and current-dependent measurements indicate a moderate increase in dynamic RDS-ON due to charge trapping and hot carrier injection, which stabilizes at higher voltages. These results highlight the feasibility of paralleling GaN HEMTs in a cascode configuration to enhance performance, reliability, and scalability in high-power applications.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"303 ","pages":"Article 112439"},"PeriodicalIF":3.1,"publicationDate":"2025-12-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145925220","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-30DOI: 10.1016/j.mee.2025.112441
Mugdha Sharma , Pradeep Dixit , Sanjeev Manhas
Through-glass vias (TGVs) are gaining importance in 2.5D/3D packaging due to their low electrical loss, dimensional stability, and panel-level manufacturability. However, the large mismatch in coefficient of thermal expansion (CTE) between copper(Cu) and glass induces significant thermo-mechanical stresses during temperature variations, leading to crack initiation, energy release, and electrical degradation. In this work, a coupled finite element method (FEM) and fracture mechanics framework is developed to analyze the reliability of Cu-filled TGVs. The study evaluates stress distribution, deformation, and current density in the presence of cracks positioned at different locations within the via and along the Cu–glass interface. The fracture driving force is quantified using the Energy Release Rate (ERR), with analytical formulations validated against FEM-based J-integral calculations. Results show that ERR scales linearly with via diameter and quadratically with temperature change magnitude, with peak values occurring when the crack length is approximately one-fourth of the via diameter. Substrate material strongly influences reliability, as fused silica produces the highest stresses and ERR, while ceramic glass gives better reliability. The introduction of polymer buffer layers significantly reduces stress in the TGV, demonstrating their effectiveness in mitigating mismatch-induced failures. Altogether, the combined FEM–ERR framework provides a unified basis for linking stress, fracture, and electrical degradation, and offers practical design guidelines for optimizing TGV-based interposers.
{"title":"Effect of thermally-induced cracks on the mechanical and electrical behaviour of TGVs","authors":"Mugdha Sharma , Pradeep Dixit , Sanjeev Manhas","doi":"10.1016/j.mee.2025.112441","DOIUrl":"10.1016/j.mee.2025.112441","url":null,"abstract":"<div><div>Through-glass vias (TGVs) are gaining importance in 2.5D/3D packaging due to their low electrical loss, dimensional stability, and panel-level manufacturability. However, the large mismatch in coefficient of thermal expansion (CTE) between copper(Cu) and glass induces significant thermo-mechanical stresses during temperature variations, leading to crack initiation, energy release, and electrical degradation. In this work, a coupled finite element method (FEM) and fracture mechanics framework is developed to analyze the reliability of Cu-filled TGVs. The study evaluates stress distribution, deformation, and current density in the presence of cracks positioned at different locations within the via and along the Cu–glass interface. The fracture driving force is quantified using the Energy Release Rate (ERR), with analytical formulations validated against FEM-based J-integral calculations. Results show that ERR scales linearly with via diameter and quadratically with temperature change magnitude, with peak values occurring when the crack length is approximately one-fourth of the via diameter. Substrate material strongly influences reliability, as fused silica produces the highest stresses and ERR, while ceramic glass gives better reliability. The introduction of polymer buffer layers significantly reduces stress in the TGV, demonstrating their effectiveness in mitigating mismatch-induced failures. Altogether, the combined FEM–ERR framework provides a unified basis for linking stress, fracture, and electrical degradation, and offers practical design guidelines for optimizing TGV-based interposers.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"304 ","pages":"Article 112441"},"PeriodicalIF":3.1,"publicationDate":"2025-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145940571","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-30DOI: 10.1016/j.mee.2025.112443
So-Yeon Kwon, Woon-San Ko, Ki-Nam Kim, Jun-Ho Byun, Do-Yeon Lee, Hi-Deok Lee, Ga-Won Lee
In this study, the structure with a graphene interlayer in a ZnO/HfO2 bilayer Resistive Random-Access Memory (RRAM) is proposed. Two types of devices were fabricated to compare the effect of graphene interlayer: one with a TiN/Ti/graphene Top Electrode (TE) device and another with a TiN/Ti TE device. The condition of the single-layer graphene was confirmed using Raman spectroscopy. The TiN/Ti/graphene TE device demonstrates an enhanced uniformity of both the set voltage (Vset) and reset voltage (Vreset). The window for the switching voltage decreases by 2.1 V, and the average on/off ratio increases by 20.09 times. The structure also exhibits self-compliance characteristics. These results highlight both the advantages of the graphene interlayer and the oxygen-scavenging properties of TiN/Ti TE. Detailed mechanisms of oxygen ion blocking by graphene interlayer are analyzed using the standard Gibbs free energy of formation (∆Gf°). The switching characteristics are analyzed by the structure's work function. And the conduction mechanism is analyzed by the space-charge limited current (SCLC), related to traps.
{"title":"Resistive switching characteristics of ZnO/HfO2 RRAM using TiN/Ti electrode with a graphene interlayer","authors":"So-Yeon Kwon, Woon-San Ko, Ki-Nam Kim, Jun-Ho Byun, Do-Yeon Lee, Hi-Deok Lee, Ga-Won Lee","doi":"10.1016/j.mee.2025.112443","DOIUrl":"10.1016/j.mee.2025.112443","url":null,"abstract":"<div><div>In this study, the structure with a graphene interlayer in a ZnO/HfO<sub>2</sub> bilayer Resistive Random-Access Memory (RRAM) is proposed. Two types of devices were fabricated to compare the effect of graphene interlayer: one with a TiN/Ti/graphene Top Electrode (TE) device and another with a TiN/Ti TE device. The condition of the single-layer graphene was confirmed using Raman spectroscopy. The TiN/Ti/graphene TE device demonstrates an enhanced uniformity of both the set voltage (V<sub>set</sub>) and reset voltage (V<sub>reset</sub>). The window for the switching voltage decreases by 2.1 V, and the average on/off ratio increases by 20.09 times. The structure also exhibits self-compliance characteristics. These results highlight both the advantages of the graphene interlayer and the oxygen-scavenging properties of TiN/Ti TE. Detailed mechanisms of oxygen ion blocking by graphene interlayer are analyzed using the standard Gibbs free energy of formation (∆G<sub>f</sub>°). The switching characteristics are analyzed by the structure's work function. And the conduction mechanism is analyzed by the space-charge limited current (SCLC), related to traps.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"303 ","pages":"Article 112443"},"PeriodicalIF":3.1,"publicationDate":"2025-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145884161","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-13DOI: 10.1016/j.mee.2025.112437
J. Martin-Martinez , N. Baghban-Bousari , R. Castro-Lopez , D. Eric , E. Roca , R. Rodriguez , M. Porti , F.V. Fernandez , M. Nafria
This work presents a statistical analysis of Random Telegraph Noise (RTN) in nanoscale MOSFETs, from more than 13,000 traces measured under varying voltages, temperatures, and bias times on an array-based characterization chip. Using the Weighted Time Lag Plot (WTLP), we extracted the average number of detectable traps and the associated current step amplitudes. Results show that the average number of detectable traps increases with voltage and temperature but decreases after some bias time due to a transient trap population. The average current step amplitude grows with voltage and shows negligible dependence on temperature. These findings support improved RTN modeling and are relevant for both reliability analysis and cryptographic applications.
{"title":"Comprehensive statistical analysis of random telegraph noise: Impact of gate voltage, temperature, and Bias time","authors":"J. Martin-Martinez , N. Baghban-Bousari , R. Castro-Lopez , D. Eric , E. Roca , R. Rodriguez , M. Porti , F.V. Fernandez , M. Nafria","doi":"10.1016/j.mee.2025.112437","DOIUrl":"10.1016/j.mee.2025.112437","url":null,"abstract":"<div><div>This work presents a statistical analysis of Random Telegraph Noise (RTN) in nanoscale MOSFETs, from more than 13,000 traces measured under varying voltages, temperatures, and bias times on an array-based characterization chip. Using the Weighted Time Lag Plot (WTLP), we extracted the average number of detectable traps and the associated current step amplitudes. Results show that the average number of detectable traps increases with voltage and temperature but decreases after some bias time due to a transient trap population. The average current step amplitude grows with voltage and shows negligible dependence on temperature. These findings support improved RTN modeling and are relevant for both reliability analysis and cryptographic applications.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"303 ","pages":"Article 112437"},"PeriodicalIF":3.1,"publicationDate":"2025-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145748013","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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