{"title":"A 20-Gb/s 4-tap time-domain DFE with pulse width modulation for a DQ-DQS matched parallel receiver","authors":"Daehoon Na, Woo-Seok Choi, Seon-Kyoo Lee","doi":"10.1049/ell2.13279","DOIUrl":null,"url":null,"abstract":"<p>A 4-tap time-domain decision feedback equalizer (TD-DFE) is presented to implement a multi-tap DFE in a matched DQ (data)-DQS (strobe) tree architecture. Traditionally, matched architecture holds an advantage in terms of power noise immunity, but it suffers from low-speed performance due to the unavailability of decision feedback equalizer (DFE) applications. By adopting the proposed TD-DFE, both high-speed operation and power noise immunity can be achieved within the matched architecture. An 8-DQ parallel receiver with the proposed 4-tap TD-DFE, designed in 28 nm CMOS, achieves a data rate of 20 Gb/s with 0.6 UI eye-opening even with 215 mV power fluctuations.</p>","PeriodicalId":11556,"journal":{"name":"Electronics Letters","volume":null,"pages":null},"PeriodicalIF":0.7000,"publicationDate":"2024-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1049/ell2.13279","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Electronics Letters","FirstCategoryId":"5","ListUrlMain":"https://onlinelibrary.wiley.com/doi/10.1049/ell2.13279","RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q4","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
A 4-tap time-domain decision feedback equalizer (TD-DFE) is presented to implement a multi-tap DFE in a matched DQ (data)-DQS (strobe) tree architecture. Traditionally, matched architecture holds an advantage in terms of power noise immunity, but it suffers from low-speed performance due to the unavailability of decision feedback equalizer (DFE) applications. By adopting the proposed TD-DFE, both high-speed operation and power noise immunity can be achieved within the matched architecture. An 8-DQ parallel receiver with the proposed 4-tap TD-DFE, designed in 28 nm CMOS, achieves a data rate of 20 Gb/s with 0.6 UI eye-opening even with 215 mV power fluctuations.
期刊介绍:
Electronics Letters is an internationally renowned peer-reviewed rapid-communication journal that publishes short original research papers every two weeks. Its broad and interdisciplinary scope covers the latest developments in all electronic engineering related fields including communication, biomedical, optical and device technologies. Electronics Letters also provides further insight into some of the latest developments through special features and interviews.
Scope
As a journal at the forefront of its field, Electronics Letters publishes papers covering all themes of electronic and electrical engineering. The major themes of the journal are listed below.
Antennas and Propagation
Biomedical and Bioinspired Technologies, Signal Processing and Applications
Control Engineering
Electromagnetism: Theory, Materials and Devices
Electronic Circuits and Systems
Image, Video and Vision Processing and Applications
Information, Computing and Communications
Instrumentation and Measurement
Microwave Technology
Optical Communications
Photonics and Opto-Electronics
Power Electronics, Energy and Sustainability
Radar, Sonar and Navigation
Semiconductor Technology
Signal Processing
MIMO