{"title":"A High-Throughput Constructive Interference Precoder for 16 × MU-MIMO Systems","authors":"Yu-Cheng Lin;Ren-Hao Chiou;Chia-Hsiang Yang","doi":"10.1109/TVLSI.2024.3423341","DOIUrl":null,"url":null,"abstract":"In a multiuser multiple-input multiple-output (MU-MIMO) downlink system, users are susceptible to interuser interference (IUI) because of data being simultaneously transmitted over the same time-frequency resources. Conventionally, precoding algorithms aim to eliminate the IUI. However, constructive interference (CI) precoding can achieve better error performance by exploiting the IUI. This article presents a high-throughput CI precoder. Design optimization across the algorithm and the architecture layers is conducted, reducing the complexity for multiplications by 81.6%. As the number of iterations for convergence varies, dynamic resource allocation is utilized to support each modulation mode with maximized utilization: time-multiplexing for the 4-QAM mode and parallel-processing for the 16-QAM mode. The proposed symbol updater also allows more efficient scheduling. As a proof of concept, a CI precoder chip that supports up to \n<inline-formula> <tex-math>$16 \\times $ </tex-math></inline-formula>\n MU-MIMO systems is designed based in a 40-nm CMOS technology. The performance gains at a bit error rate (BER) \n<inline-formula> <tex-math>$= 10^{-4}$ </tex-math></inline-formula>\n are 10.7 and 12.5 dB for 4-QAM and 16-QAM, respectively, compared with conventional regularized zero-forcing (RZF) schemes. The precoder delivers a maximum throughput of 3.2 Gb/s at a clock frequency of 200 MHz for the \n<inline-formula> <tex-math>$16 \\times $ </tex-math></inline-formula>\n MU-MIMO configuration.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":null,"pages":null},"PeriodicalIF":2.8000,"publicationDate":"2024-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10596322/","RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
引用次数: 0
Abstract
In a multiuser multiple-input multiple-output (MU-MIMO) downlink system, users are susceptible to interuser interference (IUI) because of data being simultaneously transmitted over the same time-frequency resources. Conventionally, precoding algorithms aim to eliminate the IUI. However, constructive interference (CI) precoding can achieve better error performance by exploiting the IUI. This article presents a high-throughput CI precoder. Design optimization across the algorithm and the architecture layers is conducted, reducing the complexity for multiplications by 81.6%. As the number of iterations for convergence varies, dynamic resource allocation is utilized to support each modulation mode with maximized utilization: time-multiplexing for the 4-QAM mode and parallel-processing for the 16-QAM mode. The proposed symbol updater also allows more efficient scheduling. As a proof of concept, a CI precoder chip that supports up to
$16 \times $
MU-MIMO systems is designed based in a 40-nm CMOS technology. The performance gains at a bit error rate (BER)
$= 10^{-4}$
are 10.7 and 12.5 dB for 4-QAM and 16-QAM, respectively, compared with conventional regularized zero-forcing (RZF) schemes. The precoder delivers a maximum throughput of 3.2 Gb/s at a clock frequency of 200 MHz for the
$16 \times $
MU-MIMO configuration.
期刊介绍:
The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society.
Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels.
To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.