Scaling Challenges of Nanosheet Field-Effect Transistors Into Sub-2 nm Nodes

Abstract

The scaling of nanosheet (NS) field effect transistors (FETs) from the 12 nm gate length to the ultimate gate length of 10 nm for sub-2 nm nodes brings additional technological challenges. Here, 3D finite element Monte Carlo simulations are employed to explore how to alter the NS architecture to increase the drive current ( ${I}_{\mathrm {\mathbf { DD}}}$ ) because the gate scaling to 10 nm results in a decline of the current (by $\mathbf {10.7}$ %). ${I}_{\mathrm {\mathbf {DD}}}$ of the 10 nm gate length NS FET will increase by 11% if the maximum n-type source/drain doping reaches $1\times 10^{20} \mathrm {cm^{-3}}$ , or increase by $\mathbf {3.8}$ % if the high- $\kappa $ dielectric layer equivalent oxide thickness (EOT) is less than $\mathbf {1.0}$ nm. The reduction in the channel width below 40 nm or the reduction in the channel thickness below 5 nm will substantially decrease IDD. The sub-threshold figures of merit like the sub-threshold slope (SS) will decrease from 75 to 73 mV/dec, while the drain-induced barrier lowering (DIBL) will increase from 32 to 77 mV/V. Finally, the effect of strain to increase the drive current is strongly limited by quantum confinement. ${I}_{\mathrm {\mathbf {DD}}}$ will increase by 3% and by 14% in the 10 nm gate NS FET with the $\langle 110\rangle $ and $\langle 100\rangle $ channel orientations, respectively, when a strain of $\mathbf {0.5}$ % is applied to the channel, with a negligible increase for larger strain values ( $\mathbf {0.7}$ % and $\mathbf {1.0}$ %).