Yuika Kobayashi, H. Asai, S. Iizuka, J. Hattori, T. Ikegami, Koichi Fukuda, T. Nikuni, T. Mori
{"title":"TCAD analysis of conditions for DIBL parameter misestimation in cryogenic MOSFETs","authors":"Yuika Kobayashi, H. Asai, S. Iizuka, J. Hattori, T. Ikegami, Koichi Fukuda, T. Nikuni, T. Mori","doi":"10.35848/1347-4065/ad606d","DOIUrl":null,"url":null,"abstract":"\n The study aimed to investigate the transfer characteristics of metal-oxide-semiconductor field-effect transistors (MOSFETs) at cryogenic temperatures to elucidate the experimental conditions affecting the accurate estimation of the drain-induced barrier lowering (DIBL) parameter. Our device simulation revealed that MOSFETs featuring an underlap between the gate and source/drain edges experience a significant shift in threshold voltage (V\n t) in the low drain voltage (V\n d) region, which causes the misestimation of the DIBL parameter. This V\n t change is due to a notable increase in carrier concentration within the underlap region. To mitigate misestimation, confirming the dependence of the DIBL parameter on the linear region of V\n d serves as an effective method to ensure accurate estimation.","PeriodicalId":505044,"journal":{"name":"Japanese Journal of Applied Physics","volume":"117 17","pages":""},"PeriodicalIF":0.0000,"publicationDate":"2024-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Japanese Journal of Applied Physics","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.35848/1347-4065/ad606d","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
The study aimed to investigate the transfer characteristics of metal-oxide-semiconductor field-effect transistors (MOSFETs) at cryogenic temperatures to elucidate the experimental conditions affecting the accurate estimation of the drain-induced barrier lowering (DIBL) parameter. Our device simulation revealed that MOSFETs featuring an underlap between the gate and source/drain edges experience a significant shift in threshold voltage (V
t) in the low drain voltage (V
d) region, which causes the misestimation of the DIBL parameter. This V
t change is due to a notable increase in carrier concentration within the underlap region. To mitigate misestimation, confirming the dependence of the DIBL parameter on the linear region of V
d serves as an effective method to ensure accurate estimation.
这项研究旨在调查金属氧化物半导体场效应晶体管（MOSFET）在低温下的传输特性，以阐明影响漏极诱导势垒降低（DIBL）参数准确估算的实验条件。我们的器件仿真显示，栅极和源极/漏极边缘之间存在欠间隙的 MOSFET 在低漏极电压 (V d) 区域的阈值电压 (V t) 会发生显著变化，从而导致 DIBL 参数的错误估计。这种 V t 变化是由于迭底区内的载流子浓度显著增加所致。为了减少误估，确认 DIBL 参数对 V d 线性区域的依赖性是确保准确估算的有效方法。
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