Wafer and chip-level characterization of edge-coupled photonic integrated circuits by cascaded grating couplers and spot-size converters

Abstract

This study presents an efficient testing process for characterizing silicon photonic integrated circuits. This process utilizes a coupling structure that integrates grating couplers and spot-size converters for efficient testing both at the chip and wafer levels, respectively. By leveraging wafer-level testing to estimate the characteristics of final chip-level devices, we anticipate a reduction in testing costs. To demonstrate the validity of the proposed testing process, we fabricated and measured silicon-on-insulator ring resonator devices on both wafer and chip levels. The results showed good agreement between the two levels of measurement, validating the effectiveness of our proposed testing process.