Novel high speed low power comparators imbibing Self-cascode preamplifier technique

Abstract

This paper presents novel high speed low power comparator that can further be used in analog to digital converter (ADC) circuits for Internet of Things (IoT) applications. Both circuits employ self cascode technique in preamplifier stage of conventional comparator. The proposed comparator 1 uses a static latch in second stage whilst dynamic latch is used as second stage in proposed comparator 2 to take advantage of low power. Simulations are carried out at 90 nm CMOS technology node in Cadence Virtuoso environment. Self cascode preamplifier stage shows better gain (40 %) than conventional counterpart leading to improvement of 45 % in power with 65 % lesser delay. The mathematical formulation of the delay of proposed comparators is also put forward. Post layout simulation results for delay, power, energy and area of proposed comparator 1 are observed to be 110 ps, 65uW 78fJ/conversion energy and 151um² respectively. The corresponding data for proposed comparator 2 is 81 ps, 61uW, 56 fJ/conversion energy and 137um². These results are found to be in much better proposition than other state-of-the-art works. Additionally, the performance of conventional and proposed comparators is examined using Monte-Carlo simulations and corner analysis. The proposed comparators outperform under these analyses also.