Functionally Possible Path Delay Faults With High Functional Switching Activity

Abstract

Chip aging that results in small delay defects is one of the possible causes for silent data corruption that has been observed in large datacenters. Chip aging is exacerbated by high software workloads when the chip is deployed in a system. Small delay defects are detected by tests for path delay faults. Path delay faults are typically selected to include the longest testable paths. In addition, functionally possible paths are selected to ensure the detection of small delay defects that can cause a chip to fail during functional operation. To address chip aging, it is suggested in this brief that the longest functionally possible paths through as many lines as possible with the highest susceptibilities to aging should be targeted. A path selection procedure at the gate level is described, that uses the switching activity under functional test sequences to identify functionally possible paths that are the most susceptible to aging. Experimental results for benchmark circuits show that the length of a path and the functional switching activities for lines along the path are independent, and each criterion alone leads to the selection of different paths. The results suggest that both criteria need to be used together for path selection.