Boundless Engineering for Yield to Cope With the Complexity of High-Volume Manufacturing

Abstract

This paper describes the art of engineering work that analyzes the causes of yield degradation and contributes yield enhancement through an integrated Engineering for Yield (EFY) framework in the High-Volume Manufacturing (HVM) stage. In this phase, large volumes of wafers are monitored, and defect signatures are clustered to find systematic defects. The yield loss factors are identified through volume diagnosis and the correlation between the sorting yield and the on-chip monitoring sensor is checked. Not only anchoring the production phase analysis but stochastic vulnerabilities which are not expected in the design signoff stage could be discovered through electrical profiling (eProfiling) with Monte-Carlo simulation. This EFY framework improves HVM yield and is applied to the current HVM product portfolio and will continue to be applied to upcoming HVM products. This borderless EFY framework achieves the tangible result of improving the mature yield by >1% by resolving problems that occurred in the HVM stage within a few weeks but also contributes to preventing possible defects for the next HVM products.