Performance and Threshold Voltage Reliability of Quaternary InAlGaN/GaN MIS-HEMT on Si for Power Device Applications

IF 2.5 3区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC IEEE Transactions on Device and Materials Reliability Pub Date : 2024-07-16 DOI:10.1109/TDMR.2024.3429185
Shivendra K. Rathaur;Cheng-Jun Ma;Abhisek Dixit;Ching-Ting Lee;Edward Yi Chang
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Abstract

In this study, we empirically explore the performance degradation of quaternary InAlGaN/AlN/GaN Metal-Insulator-Semiconductor High Electron Mobility Transistors (MIS-HEMTs) with a Gate Field Plate (GFP) structure under a Positive Bias Temperature Instability (PBTI) and Negative Bias Temperature Instability (NBTI) stresses. Both stress conditions (PBTI with V ${_{\text {GS}}} = 10$ V and NBTI with V ${_{\text {GS}}} {=} -30$ V) are applied. The experimental findings reveal a positive shift in threshold voltage (VTH), indicating the presence of a net negative charge beneath the gate area. However, we find distinct degradation dynamics for both stress experiments. During PBTI, the ${\mathrm { V}}_{\mathrm { TH}}$ shift remains temperature independent, suggesting the generation of defects leading to electron trapping in the insulator. In NBTI, critical defects are identified, resulting in a permanent ${\mathrm { V}}_{\mathrm { TH}}$ shift with temperature dependence. Furthermore, the extracted activation energy (Ea) from Arrhenius plots in PBTI is determined to be 0.14 eV and 0.11 eV, highlighting the crucial role of shallow C-related traps governed by the Shockley-Read Hall (SRH) recombination process. In contrast, for NBTI, ${\mathrm { E}}_{\mathrm { a}} = 0.12$ eV, indicating the involvement of surface traps and thermal-assisted de-trapping kinetics, leading to the generation of permanent defects. These results underscore the distinct dynamics of performance degradation phenomena in PBTI and NBTI involves different trap energies at different locations within the device structure.
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用于功率器件应用的硅基四元 InAlGaN/GaN MIS-HEMT 的性能和阈值电压可靠性
在本研究中,我们根据经验探讨了具有栅极场板(GFP)结构的四元 InAlGaN/AlN/GaN 金属绝缘体-半导体高电子迁移率晶体管(MIS-HEMT)在正偏置温度不稳定性(PBTI)和负偏置温度不稳定性(NBTI)应力条件下的性能退化。两种应力条件(PBTI 条件下 V ${_{\text {GS}} = 10$ V 和 NBTI 条件下 V ${_{\text {GS}}{=}-30$ V)。实验结果表明,阈值电压 (VTH) 发生了正向移动,表明栅极区域下方存在净负电荷。然而,我们发现两种应力实验的降解动态截然不同。在 PBTI 期间,${\mathrm { V}}_{\mathrm { TH}}$ 移动与温度无关,这表明缺陷的产生导致了绝缘体中的电子捕获。在 NBTI 中,临界缺陷被识别出来,导致永久的 ${\mathrm { V}_{\mathrm { TH}}$ 漂移与温度有关。此外,在 PBTI 中,从阿伦尼乌斯图中提取的活化能(Ea)被确定为 0.14 eV 和 0.11 eV,这突出了由肖克利-雷德霍尔(SRH)重组过程控制的浅 C 相关陷阱的关键作用。相反,对于 NBTI,${\mathrm { E}}_{\mathrm { a}} = 0.12$ eV,这表明表面陷阱和热辅助去陷阱动力学的参与导致了永久缺陷的产生。这些结果强调了 PBTI 和 NBTI 中性能退化现象的不同动态,涉及器件结构内不同位置的不同陷阱能量。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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来源期刊
IEEE Transactions on Device and Materials Reliability
IEEE Transactions on Device and Materials Reliability 工程技术-工程:电子与电气
CiteScore
4.80
自引率
5.00%
发文量
71
审稿时长
6-12 weeks
期刊介绍: The scope of the publication includes, but is not limited to Reliability of: Devices, Materials, Processes, Interfaces, Integrated Microsystems (including MEMS & Sensors), Transistors, Technology (CMOS, BiCMOS, etc.), Integrated Circuits (IC, SSI, MSI, LSI, ULSI, ELSI, etc.), Thin Film Transistor Applications. The measurement and understanding of the reliability of such entities at each phase, from the concept stage through research and development and into manufacturing scale-up, provides the overall database on the reliability of the devices, materials, processes, package and other necessities for the successful introduction of a product to market. This reliability database is the foundation for a quality product, which meets customer expectation. A product so developed has high reliability. High quality will be achieved because product weaknesses will have been found (root cause analysis) and designed out of the final product. This process of ever increasing reliability and quality will result in a superior product. In the end, reliability and quality are not one thing; but in a sense everything, which can be or has to be done to guarantee that the product successfully performs in the field under customer conditions. Our goal is to capture these advances. An additional objective is to focus cross fertilized communication in the state of the art of reliability of electronic materials and devices and provide fundamental understanding of basic phenomena that affect reliability. In addition, the publication is a forum for interdisciplinary studies on reliability. An overall goal is to provide leading edge/state of the art information, which is critically relevant to the creation of reliable products.
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Table of Contents IEEE Transactions on Device and Materials Reliability Publication Information IEEE Transactions on Device and Materials Reliability Information for Authors Correction to “Universal Dielectric Breakdown Modeling Under Off-State TDDB for Ultra-Scaled Device From 130 nm to 28 nm Nodes and Beyond” Blank Page
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