Monolithic three-dimensional integration of complementary two-dimensional field-effect transistors

Abstract

The semiconductor industry is transitioning to the ‘More Moore’ era, driven by the adoption of three-dimensional (3D) integration schemes surpassing the limitations of traditional two-dimensional scaling. Although innovative packaging solutions have made 3D integrated circuits (ICs) commercially viable, the inclusion of through-silicon vias and microbumps brings about increased area overhead and introduces parasitic capacitances that limit overall performance. Monolithic 3D integration (M3D) is regarded as the future of 3D ICs, yet its application faces hurdles in silicon ICs due to restricted thermal processing budgets in upper tiers, which can degrade device performance. To overcome these limitations, emerging materials like carbon nanotubes and two-dimensional semiconductors have been integrated into the back end of silicon ICs. Here we report the M3D integration of complementary WSe2 FETs, in which n-type FETs are placed in tier 1 and p-type FETs are placed in tier 2. In particular, we achieve dense and scaled integration through 300 nm vias with a pitch of <1 µm, connecting more than 300 devices in tiers 1 and 2. Moreover, we have effectively implemented vertically integrated logic gates, encompassing inverters, NAND gates and NOR gates. Our demonstration highlights the two-dimensional materials’ role in advancing M3D integration in complementary metal–oxide–semiconductor circuits. Monolithic 3D integration of complementary WSe2 FETs has been achieved, featuring n-type FETs in tier 1 and p-type FETs in tier 2. Dense vias are realized using a pitch of less than 1 µm, facilitating 3D inverters as well as NAND and NOR logic functionalities.