Design Space Optimization for Eradication of NDR Effect in Dielectric/Ferroelectric-Stacked Negative Capacitance Multigate FETs at Sub-3 nm Technology for Digital/ Analog/RF Applications
{"title":"Design Space Optimization for Eradication of NDR Effect in Dielectric/Ferroelectric-Stacked Negative Capacitance Multigate FETs at Sub-3 nm Technology for Digital/ Analog/RF Applications","authors":"Sresta Valasa;Venkata Ramakrishna Kotha;Shubham Tayal;Narendar Vadthiya","doi":"10.1109/TDEI.2024.3432088","DOIUrl":null,"url":null,"abstract":"In this study, for the first time we benchmark the dc/analog/RF performance of dielectric/ferroelectric (FE)-stacked negative capacitance (NC)-based multigate devices, including FinFETs, nanowire (NW)FETs, and nanosheet (NS)FETs, at the sub-3 nm technology node’s ultimate scaling limit involving a fully calibrated 3-D TCAD simulation. Exploring a design space to eliminate negative differential resistance (NDR) and optimize performance, we varied parameters such as gate length (<inline-formula> <tex-math>${L}_{\\text {g}}\\text {)}$ </tex-math></inline-formula>, fin thickness (<inline-formula> <tex-math>${T}_{\\text {fin}}\\text {)}$ </tex-math></inline-formula>, fin height (<inline-formula> <tex-math>${H}_{\\text {fin}}\\text {)}$ </tex-math></inline-formula>, NW diameter (<inline-formula> <tex-math>${D}_{\\text {NW}}\\text {)}$ </tex-math></inline-formula>, NS width (<inline-formula> <tex-math>${W}_{\\text {NS}}\\text {)}$ </tex-math></inline-formula>, and NS thickness (<inline-formula> <tex-math>${T}_{\\text {NS}}\\text {)}$ </tex-math></inline-formula>. The analysis shows that the NC-NSFET outperforms NC-FinFET, exhibiting an improved SS, enhanced intrinsic gain (<inline-formula> <tex-math>${A}_{\\text {V}}\\text {)}$ </tex-math></inline-formula> of ~15% and a <inline-formula> <tex-math>$3\\times $ </tex-math></inline-formula> improvement in cut-off frequency (<inline-formula> <tex-math>${f}_{\\text {T}}\\text {)}$ </tex-math></inline-formula>. Notably, NDR effects were observed for <inline-formula> <tex-math>${L}_{\\text {g}} \\lt 15$ </tex-math></inline-formula> nm in all devices and for NC-FinFET, downsizing <inline-formula> <tex-math>${T}_{\\text {fin}}$ </tex-math></inline-formula> and <inline-formula> <tex-math>${H}_{\\text {fin}} \\lt 5$ </tex-math></inline-formula> nm and <30> <tex-math>${T}_{\\text {NS}}$ </tex-math></inline-formula> and <inline-formula> <tex-math>${W}_{\\text {NS}} \\lt 5$ </tex-math></inline-formula> nm and <18> <tex-math>${L}_{\\text {g}}$ </tex-math></inline-formula>, the <inline-formula> <tex-math>${f}_{\\text {T}}$ </tex-math></inline-formula> is noticed to be improved by an amount of ~6.6%, ~17.4%, and ~23.7% for NC-FinFET, NC-NWFET, and NC-NSFET, respectively, with better performance noticed for NC-NSFET. By downscaling the <inline-formula> <tex-math>${T}_{\\text {fin}}$ </tex-math></inline-formula> to <inline-formula> <tex-math>$\\sim 3.6\\times $ </tex-math></inline-formula>, the <inline-formula> <tex-math>${A}_{\\text {V}}$ </tex-math></inline-formula> and <inline-formula> <tex-math>${f}_{\\text {T}}$ </tex-math></inline-formula> is found to be improved by ~42.6% and ~21.5%, respectively. However, scaling the <inline-formula> <tex-math>${H}_{\\text {fin}}$ </tex-math></inline-formula> resulted in better improvement in fT by ~48.47%. By downscaling the <inline-formula> <tex-math>${T}_{\\text {NS}}$ </tex-math></inline-formula>, the <inline-formula> <tex-math>${A}_{\\text {V}}$ </tex-math></inline-formula> and <inline-formula> <tex-math>${f}_{\\text {T}}$ </tex-math></inline-formula> are improved by ~28.13% and ~46.19% while scaling the <inline-formula> <tex-math>${W}_{\\text {NS}}$ </tex-math></inline-formula>, the <inline-formula> <tex-math>${f}_{\\text {T}}$ </tex-math></inline-formula> is improved by ~45.96%. Overall, this research establishes the NC-NSFET as a frontrunner proving itself as the optimal choice for analog/RF applications in the realm of nanoscale semiconductor technology.","PeriodicalId":13247,"journal":{"name":"IEEE Transactions on Dielectrics and Electrical Insulation","volume":"32 2","pages":"769-778"},"PeriodicalIF":3.1000,"publicationDate":"2024-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Dielectrics and Electrical Insulation","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10606247/","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
In this study, for the first time we benchmark the dc/analog/RF performance of dielectric/ferroelectric (FE)-stacked negative capacitance (NC)-based multigate devices, including FinFETs, nanowire (NW)FETs, and nanosheet (NS)FETs, at the sub-3 nm technology node’s ultimate scaling limit involving a fully calibrated 3-D TCAD simulation. Exploring a design space to eliminate negative differential resistance (NDR) and optimize performance, we varied parameters such as gate length (${L}_{\text {g}}\text {)}$ , fin thickness (${T}_{\text {fin}}\text {)}$ , fin height (${H}_{\text {fin}}\text {)}$ , NW diameter (${D}_{\text {NW}}\text {)}$ , NS width (${W}_{\text {NS}}\text {)}$ , and NS thickness (${T}_{\text {NS}}\text {)}$ . The analysis shows that the NC-NSFET outperforms NC-FinFET, exhibiting an improved SS, enhanced intrinsic gain (${A}_{\text {V}}\text {)}$ of ~15% and a $3\times $ improvement in cut-off frequency (${f}_{\text {T}}\text {)}$ . Notably, NDR effects were observed for ${L}_{\text {g}} \lt 15$ nm in all devices and for NC-FinFET, downsizing ${T}_{\text {fin}}$ and ${H}_{\text {fin}} \lt 5$ nm and <30> ${T}_{\text {NS}}$ and ${W}_{\text {NS}} \lt 5$ nm and <18> ${L}_{\text {g}}$ , the ${f}_{\text {T}}$ is noticed to be improved by an amount of ~6.6%, ~17.4%, and ~23.7% for NC-FinFET, NC-NWFET, and NC-NSFET, respectively, with better performance noticed for NC-NSFET. By downscaling the ${T}_{\text {fin}}$ to $\sim 3.6\times $ , the ${A}_{\text {V}}$ and ${f}_{\text {T}}$ is found to be improved by ~42.6% and ~21.5%, respectively. However, scaling the ${H}_{\text {fin}}$ resulted in better improvement in fT by ~48.47%. By downscaling the ${T}_{\text {NS}}$ , the ${A}_{\text {V}}$ and ${f}_{\text {T}}$ are improved by ~28.13% and ~46.19% while scaling the ${W}_{\text {NS}}$ , the ${f}_{\text {T}}$ is improved by ~45.96%. Overall, this research establishes the NC-NSFET as a frontrunner proving itself as the optimal choice for analog/RF applications in the realm of nanoscale semiconductor technology.
期刊介绍:
Topics that are concerned with dielectric phenomena and measurements, with development and characterization of gaseous, vacuum, liquid and solid electrical insulating materials and systems; and with utilization of these materials in circuits and systems under condition of use.