Design Space Optimization for Eradication of NDR Effect in Dielectric/Ferroelectric-Stacked Negative Capacitance Multigate FETs at Sub-3 nm Technology for Digital/ Analog/RF Applications

IF 3.1 3区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC IEEE Transactions on Dielectrics and Electrical Insulation Pub Date : 2024-07-22 DOI:10.1109/TDEI.2024.3432088
Sresta Valasa;Venkata Ramakrishna Kotha;Shubham Tayal;Narendar Vadthiya
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Abstract

In this study, for the first time we benchmark the dc/analog/RF performance of dielectric/ferroelectric (FE)-stacked negative capacitance (NC)-based multigate devices, including FinFETs, nanowire (NW)FETs, and nanosheet (NS)FETs, at the sub-3 nm technology node’s ultimate scaling limit involving a fully calibrated 3-D TCAD simulation. Exploring a design space to eliminate negative differential resistance (NDR) and optimize performance, we varied parameters such as gate length ( ${L}_{\text {g}}\text {)}$ , fin thickness ( ${T}_{\text {fin}}\text {)}$ , fin height ( ${H}_{\text {fin}}\text {)}$ , NW diameter ( ${D}_{\text {NW}}\text {)}$ , NS width ( ${W}_{\text {NS}}\text {)}$ , and NS thickness ( ${T}_{\text {NS}}\text {)}$ . The analysis shows that the NC-NSFET outperforms NC-FinFET, exhibiting an improved SS, enhanced intrinsic gain ( ${A}_{\text {V}}\text {)}$ of ~15% and a $3\times $ improvement in cut-off frequency ( ${f}_{\text {T}}\text {)}$ . Notably, NDR effects were observed for ${L}_{\text {g}} \lt 15$ nm in all devices and for NC-FinFET, downsizing ${T}_{\text {fin}}$ and ${H}_{\text {fin}} \lt 5$ nm and <30> ${T}_{\text {NS}}$ and ${W}_{\text {NS}} \lt 5$ nm and <18> ${L}_{\text {g}}$ , the ${f}_{\text {T}}$ is noticed to be improved by an amount of ~6.6%, ~17.4%, and ~23.7% for NC-FinFET, NC-NWFET, and NC-NSFET, respectively, with better performance noticed for NC-NSFET. By downscaling the ${T}_{\text {fin}}$ to $\sim 3.6\times $ , the ${A}_{\text {V}}$ and ${f}_{\text {T}}$ is found to be improved by ~42.6% and ~21.5%, respectively. However, scaling the ${H}_{\text {fin}}$ resulted in better improvement in fT by ~48.47%. By downscaling the ${T}_{\text {NS}}$ , the ${A}_{\text {V}}$ and ${f}_{\text {T}}$ are improved by ~28.13% and ~46.19% while scaling the ${W}_{\text {NS}}$ , the ${f}_{\text {T}}$ is improved by ~45.96%. Overall, this research establishes the NC-NSFET as a frontrunner proving itself as the optimal choice for analog/RF applications in the realm of nanoscale semiconductor technology.
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优化设计空间,消除 3 纳米以下技术中用于数字/模拟/射频应用的介电/费电叠层负电容多栅极场效应晶体管中的 NDR 效应
在这项研究中,我们首次对介电/铁电(FE)堆叠负电容(NC)的多栅极器件(包括finfet、纳米线(NW) fet和纳米片(NS) fet)的dc/模拟/RF性能进行了基准测试,测试涉及完全校准的3-D TCAD模拟。为了探索消除负微分电阻(NDR)和优化性能的设计空间,我们改变了栅极长度(${L}_{\text {g}}\text{)}$、鳍片厚度(${T}_{\text {g}}\text{)}$、鳍片高度(${H}_{\text {fin}}\text{)}$、NW直径(${D}_{\text {NW}}\text{)}$、NS宽度(${W}_{\text {NS}}\text{)}$和NS厚度(${T}_{\text {NS}}\text{)}$。分析表明,NC-NSFET优于NC-FinFET,表现出改进的SS,增强的内在增益(${A}_{\text {V}}\text{)}$提高了约15%,截止频率(${f}_{\text {T}}\text{)}$提高了$3倍。值得注意的是,在所有器件中${L}_{\text {g}} \lt 15$ nm处观察到NDR效应,对于NC-FinFET,减小${T}_{\text {fin}}$和${H}_{\text {fin}}}$和${T}_{\text {NS}}$和${W}_{\text {NS}}}$ 5$ nm和${L}_ \text {n}}}$时,NC-FinFET、NC-NWFET和NC-NSFET的${f}_{\text {T}}$分别提高了~6.6%、~17.4%和~23.7%,其中NC-NSFET性能更好。通过将${T}_{\text {fin}}$缩小到$\sim的3.6倍$,${A}_{\text {V}}$和${f}_{\text {T}}$分别提高了~42.6%和~21.5%。然而,缩放${H}_{\text {fin}}$导致fT更好地提高了~48.47%。通过缩小${T}_{\text {NS}}$, ${A}_{\text {V}}$和${f}_{\text {T}}$的性能分别提高了~28.13%和~46.19%;缩小${W}_{\text {NS}}$的性能,${f}_{\text {T}}$的性能提高了~45.96%。总体而言,本研究确立了NC-NSFET作为纳米级半导体技术领域模拟/射频应用的最佳选择的领跑者地位。
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来源期刊
IEEE Transactions on Dielectrics and Electrical Insulation
IEEE Transactions on Dielectrics and Electrical Insulation 工程技术-工程:电子与电气
CiteScore
6.00
自引率
22.60%
发文量
309
审稿时长
5.2 months
期刊介绍: Topics that are concerned with dielectric phenomena and measurements, with development and characterization of gaseous, vacuum, liquid and solid electrical insulating materials and systems; and with utilization of these materials in circuits and systems under condition of use.
期刊最新文献
IEEE Transactions on Dielectrics and Electrical Insulation Information for Authors Corrections to “On the Frequency Dependence of the PDIV in Twisted Pair Magnet Wire Analogy in Dry Air” IEEE Dielectrics and Electrical Insulation Society Information 2025 Index IEEE Transactions on Dielectrics and Electrical Insulation IEEE Transactions on Dielectrics and Electrical Insulation Information for Authors
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