Shouharda Ghosh;Pramod Kumar Meher;Dwaipayan Ray;Nithin V. George
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引用次数: 0
Abstract
In many practical scenarios, non-Gaussian noise contaminates the desired signal and introduces outliers. The recently proposed logistic distance metric adaptive filter (LDMAF) outperforms the existing algorithms and provides better performance in the presence of such outliers. There is a need for efficient hardware architecture for the implementation of LDMAF. This article proposes an efficient VLSI architecture of LDMAF. The implementation of error-gradient function of LDMAF puts significant implementation problem in terms of delay and cost. We introduce here an efficient tangent-based piecewise linear (TPL) approximation algorithm for implementing the corresponding architecture. The proposed approach improves the power, performance, and area (PPA) metrics over state-of-the-art implementations of other robust algorithms while meeting system performance within an acceptable deviation.
期刊介绍:
The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society.
Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels.
To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.