Low Complexity Design of Logistic Distance Metric Adaptive Filter for Impulsive Noise Environments

IF 2.8 2区 工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-06-11 DOI:10.1109/TVLSI.2024.3407732
Shouharda Ghosh;Pramod Kumar Meher;Dwaipayan Ray;Nithin V. George
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Abstract

In many practical scenarios, non-Gaussian noise contaminates the desired signal and introduces outliers. The recently proposed logistic distance metric adaptive filter (LDMAF) outperforms the existing algorithms and provides better performance in the presence of such outliers. There is a need for efficient hardware architecture for the implementation of LDMAF. This article proposes an efficient VLSI architecture of LDMAF. The implementation of error-gradient function of LDMAF puts significant implementation problem in terms of delay and cost. We introduce here an efficient tangent-based piecewise linear (TPL) approximation algorithm for implementing the corresponding architecture. The proposed approach improves the power, performance, and area (PPA) metrics over state-of-the-art implementations of other robust algorithms while meeting system performance within an acceptable deviation.
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针对脉冲噪声环境的逻辑距离度量自适应滤波器的低复杂度设计
在许多实际场景中,非高斯噪声会污染所需的信号并引入异常值。最近提出的逻辑距离度量自适应滤波器(LDMAF)性能优于现有算法,在出现此类异常值时能提供更好的性能。实现 LDMAF 需要高效的硬件架构。本文提出了一种高效的 LDMAF VLSI 架构。LDMAF 的误差梯度函数的实现在延迟和成本方面存在很大的问题。我们在此引入了一种高效的基于切线的分片线性(TPL)近似算法来实现相应的架构。与其他鲁棒算法的最先进实现方法相比,所提出的方法提高了功耗、性能和面积(PPA)指标,同时将系统性能控制在可接受的偏差范围内。
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来源期刊
CiteScore
6.40
自引率
7.10%
发文量
187
审稿时长
3.6 months
期刊介绍: The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.
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