{"title":"Design and Analysis of a New Three-Stage Feedback Amplifier Utilizing Signal Flow Graph Domain Inspection Approach","authors":"M. Ghashghai;M. B. Ghaznavi-Ghoushchi","doi":"10.1109/TVLSI.2024.3426516","DOIUrl":null,"url":null,"abstract":"In this article, the design strategy with the analysis in the graph domain and changing the signal flow graph (SFG) of an amplifier are employed according to the graph rules at the system level. A three-stage amplifier, which expands the dual-path structure and buffering-based pole relocation amplifier through the graph domain inspection by using the graph rules, is proposed. By adding order of denominator in main fraction of the equivalent impedance of active zero block, the proposed amplifier can effectively increase the driving ability while enhancing the amplifier’s stability for a large range of capacitive load. The second pole is located at a higher frequency to increase the phase margin (PM). Circuit implementation of the proposed amplifier is simulated in 0.18-\n<inline-formula> <tex-math>$\\mu $ </tex-math></inline-formula>\n CMOS standard technology with 0.004-mm2 active area and 8.8-\n<inline-formula> <tex-math>$\\mu $ </tex-math></inline-formula>\n power consumption. Post-layout simulation results show 130 dB in dc gain, with a 670-kHz unity-gain frequency, while the amplifier uses a 400-fF compensation capacitor. The amplifier has obtained a PM of 60.4° at C\n<inline-formula> <tex-math>$_{\\text {L}} =3.7$ </tex-math></inline-formula>\n nF. An average slew rate (SR) of 0.38 v/\n<inline-formula> <tex-math>$\\mu $ </tex-math></inline-formula>\n s was measured when the proposed amplifier was in unity-gain configuration to drive a 3.7-nF load capacitor. FoMS and FoML in the proposed amplifier are improved by 116% and 107%, respectively.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"32 10","pages":"1792-1800"},"PeriodicalIF":2.8000,"publicationDate":"2024-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10609834/","RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
引用次数: 0
Abstract
In this article, the design strategy with the analysis in the graph domain and changing the signal flow graph (SFG) of an amplifier are employed according to the graph rules at the system level. A three-stage amplifier, which expands the dual-path structure and buffering-based pole relocation amplifier through the graph domain inspection by using the graph rules, is proposed. By adding order of denominator in main fraction of the equivalent impedance of active zero block, the proposed amplifier can effectively increase the driving ability while enhancing the amplifier’s stability for a large range of capacitive load. The second pole is located at a higher frequency to increase the phase margin (PM). Circuit implementation of the proposed amplifier is simulated in 0.18-
$\mu $
CMOS standard technology with 0.004-mm2 active area and 8.8-
$\mu $
power consumption. Post-layout simulation results show 130 dB in dc gain, with a 670-kHz unity-gain frequency, while the amplifier uses a 400-fF compensation capacitor. The amplifier has obtained a PM of 60.4° at C
$_{\text {L}} =3.7$
nF. An average slew rate (SR) of 0.38 v/
$\mu $
s was measured when the proposed amplifier was in unity-gain configuration to drive a 3.7-nF load capacitor. FoMS and FoML in the proposed amplifier are improved by 116% and 107%, respectively.
期刊介绍：
The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society.
Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels.
To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.
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