Design of Octave Tuning Range LC VCO With Ultralow KVCO Using Frequency-Dependent Implicit Capacitance Neutralization Technique

IF 2.8 2区 工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-07-25 DOI:10.1109/TVLSI.2024.3430544
Youming Zhang;Xusheng Tang;Tonglu Jiao;Peng Liu;Jingchen Liu
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Abstract

This article presents a technique of frequency-dependent implicit capacitance neutralization (FD-ICN) among capacitor bank and varactors in LC voltage-controlled oscillator (VCO) to facilitate ultralow VCO gain ( $K_{\text {VCO}}$ ) across an octave frequency tuning range (TR). Series interconnect inductors are used between capacitor units to feature the inverse capacitance-frequency (C–f) relationship with varactors, thus yielding the proposed FD-ICN. A split 8-bit capacitor bank with centrosymmetric double-cross layout pattern is designed, enabling an enhanced FD-ICN through multiple capacitance equivalent iterations of the capacitor bank. The proposed FD-ICN technique is validated in a prototype of dual-mode electric-coupling VCO and fabricated in 130-nm CMOS process, exhibiting a measured frequency TR of 72.1% from 6.49 to 13.81 GHz with a $K_{\text {VCO}}$ of 7–73 MHz/V. The VCO shows a competitive phase noise (PN) and figures-of-merit in TR (FoM $\rm {_{T}}$ ) from −121.3 to −111.4 dBc/Hz and 197.4 to 201.7 dBc/Hz at 1-MHz offset across the whole TR.
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利用频率相关隐含电容中和技术设计具有超低 $K_{\text{VCO}}$ 的倍频程调谐范围 $LC$ VCO
本文提出了一种 LC 压控振荡器(VCO)中电容器组和变容器之间的频率相关隐式电容中和(FD-ICN)技术,以促进整个倍频程频率调谐范围(TR)内的超低 VCO 增益($K_{\text {VCO}}$)。电容器单元之间使用串联互联电感器,以实现变容电容器的反电容-频率(C-f)关系,从而产生拟议的 FD-ICN。设计了一个具有中心对称双交叉布局模式的 8 位分离式电容器组,通过电容器组的多次电容等效迭代,实现了增强型 FD-ICN 。所提出的 FD-ICN 技术在双模电耦合 VCO 原型中得到了验证,该原型采用 130 纳米 CMOS 工艺制造,在 6.49 至 13.81 GHz 范围内的测量频率 TR 为 72.1%,K_{\text {VCO}}$ 为 7-73 MHz/V。在整个 TR 期间,该 VCO 显示出极具竞争力的相位噪声 (PN) 和 TR 中的优越性(FoM $\rm {_{T}}$ ),分别为 -121.3 至 -111.4 dBc/Hz,以及在 1-MHz 偏移时的 197.4 至 201.7 dBc/Hz。
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来源期刊
CiteScore
6.40
自引率
7.10%
发文量
187
审稿时长
3.6 months
期刊介绍: The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.
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