Backdoor-resistant certificateless-based message-locked integrity auditing for computing power network

IF 3.7 2区 计算机科学 Q1 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE Journal of Systems Architecture Pub Date : 2024-07-24 DOI:10.1016/j.sysarc.2024.103244
Xiaodong Yang , Lizhen Wei , Muzi Li , Xiaoni Du , Caifen Wang
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Abstract

With the evolution of 6G technology, the computing power network (CPN), a crucial infrastructure underpinning the future of digital transformation, is being tightly integrated with 6G to jointly foster significant enhancements in network performance. However, the openness of the network and the semi-trusted nature of cloud service providers pose risks to user data, including potential theft and tampering. To address these challenges, this paper introduces a novel scheme called the backdoor-resistant certificateless message-locked integrity audit (BRCLMIA). This scheme incorporates a cryptographic reverse firewall, offering an efficient and secure approach to auditing CPN data integrity. Our thorough analysis demonstrates that the BRCLMIA scheme effectively safeguards against existential forgery under adaptive message attacks, safeguards against algorithm replacement attacks, and ensures the integrity and authenticity of data transmitted within the CPN. Furthermore, the performance analysis reveals that the BRCLMIA scheme exhibits remarkable communication and computational efficiency while defending against various attacks.

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面向计算能力网络的基于无证书消息锁定的抗后门完整性审计
随着 6G 技术的发展,计算能力网络(CPN)这一支撑未来数字化转型的重要基础设施正与 6G 紧密结合,共同促进网络性能的显著提升。然而,网络的开放性和云服务提供商的半信任性质给用户数据带来了风险,包括潜在的盗窃和篡改。为了应对这些挑战,本文介绍了一种名为无后门证书信息锁定完整性审计(BRCLMIA)的新型方案。该方案结合了加密反向防火墙,提供了一种高效、安全的 CPN 数据完整性审计方法。我们的全面分析表明,BRCLMIA 方案能有效抵御自适应信息攻击下的存在性伪造,抵御算法替换攻击,并确保在 CPN 内传输的数据的完整性和真实性。此外,性能分析表明,BRCLMIA 方案在抵御各种攻击的同时,还具有显著的通信和计算效率。
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来源期刊
Journal of Systems Architecture
Journal of Systems Architecture 工程技术-计算机:硬件
CiteScore
8.70
自引率
15.60%
发文量
226
审稿时长
46 days
期刊介绍: The Journal of Systems Architecture: Embedded Software Design (JSA) is a journal covering all design and architectural aspects related to embedded systems and software. It ranges from the microarchitecture level via the system software level up to the application-specific architecture level. Aspects such as real-time systems, operating systems, FPGA programming, programming languages, communications (limited to analysis and the software stack), mobile systems, parallel and distributed architectures as well as additional subjects in the computer and system architecture area will fall within the scope of this journal. Technology will not be a main focus, but its use and relevance to particular designs will be. Case studies are welcome but must contribute more than just a design for a particular piece of software. Design automation of such systems including methodologies, techniques and tools for their design as well as novel designs of software components fall within the scope of this journal. Novel applications that use embedded systems are also central in this journal. While hardware is not a part of this journal hardware/software co-design methods that consider interplay between software and hardware components with and emphasis on software are also relevant here.
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