{"title":"Design of energy efficient N-bit vedic multiplier for low power hardware architecture","authors":"A. Sridevi, A. Sathiya","doi":"10.1080/00207217.2024.2382494","DOIUrl":null,"url":null,"abstract":"","PeriodicalId":507856,"journal":{"name":"International Journal of Electronics","volume":"5 10","pages":""},"PeriodicalIF":0.0000,"publicationDate":"2024-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Journal of Electronics","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1080/00207217.2024.2382494","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
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