A Comprehensive Study and Comparison of 2-Bit 7T–10T SRAM Configurations with 4-State CMOS-SWS Inverters

Abstract

This paper presents a comprehensive analysis of power dissipation and propagation delay in 2-bit SRAM configurations ranging from 7T to 10T, building upon previous work on 6T 2-bit/4-state SWSFET SRAM designs. The study compares the performance of SWSFET SRAMs with CMOS-based 2-state SRAMs [7], highlighting the former’s significant advantages in speed and power consumption. Utilizing Cadence simulations and models such as Analog Behavioral Model (ABM) and EKV (Enz–Krummenacher–Vittoz), the analysis incorporates real-world 0.18-[Formula: see text]m technology considerations. The research explores the design nuances of 7T–10T SRAM configurations using SWS-FETs, leveraging their unique characteristics like vertically stacked quantum well/quantum dot channels. Power dissipation analysis reveals varying trends across different SRAM configurations, with notable shifts in voltage changes during transitions. Similarly, propagation delay assessments showcase diverse durations for different voltage transitions, underscoring the impact of SRAM configuration changes on efficiency and complexity. In addition, parasitic capacitance is crucial for optimizing the performance, power efficiency, and reliability of SRAM cells. In these circuits an internal storage parasitic capacitance of 1[Formula: see text]fF has been considered to evaluate its effects through simulation-based analysis during the memory cell design process. The findings contribute valuable insights into the trade-offs involved in SRAM design, particularly concerning power dissipation and propagation delay, and are presented. Overall, this study sheds light on the promising potential of SWS-FETs for enhancing memory circuitry performance.