An 11-bit SAR ADC for high frame rate and high-dynamic X-ray imaging at future XFELs

Abstract

The paper presents the design and test results of an 11-bit successive approximation register (SAR) ADC, suitable for massive on-chip integration in a pixel readout chip. The objective is to establish new digital readout architectures for X-ray pixel detectors at future X-ray free electron laser (XFEL) facilities, enabling high frame rates and a high dynamic range simultaneously. The prototype chip has been designed and fabricated in a 130 nm CMOS process, with the core circuit occupying an area of ~ 0.034 mm2. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) are +0.78/-0.78 LSB and +0.58/-0.52 LSB, respectively. The signal-to-noise-and-distortion ratio (SINAD) is 61.6 dB at 2 MS/s, achieving an effective number of bit (ENOB) of ~ 9.94-bit. The core circuit power consumption is 47 μW at 2 MS/s with a 1.2 V supply.