An area efficient 64 point Radix-42 MDC FFT architecture for OFDM applications

Abstract

In this research,we present a 64-point radix-$4^2$ pipelined Fast Fourier Transform(FFT) architecture which is area-efficient for an orthogonal frequency division multiplexing(OFDM) based IEEE 802.11a wireless Local area network(LAN) baseband. We adopt Multiple Delay Commutator(MDC) architecture for hardware implementation. The proposed 64-point FFT adopts a modified constant multiplier to compute complex multiplication in place of complex multipliers and to avoid read-only memory(ROM),which is used to store twiddle factor coefficients internally. The area of the design is reduced by using modified constant multiplier. The proposed radix-$4^2$ pipelined FFT architecture is synthesized using 45 nm CMOS technology with a supply voltage of 1.1 V. The proposed design occupies 15.31K total gates,dissipates 8.6 mW of power and the power delay product is 430$e^{-12}$.