Fabrication Techniques for a Tuneable Room Temperature Hybrid Single-electron Transistor and Field-effect Transistor

Abstract

Hybrid room-temperature (RT) silicon single-electron – field effect transistors (SET-FETs) provide a means to switch between ‘classical’, high current FET, and low-power SET operation, using a gate voltage. While operating as a SET, charge on a silicon quantum dot (QD) within the current channel, can be controlled at the one-electron level using the Coulomb blockade effect. This paper investigates nanofabrication methods for sub-10 nm ‘fin’ channel hybrid RT SET-FETs, and their influence on the energy band diagram, and formation of tunnel barriers and QDs, along the channel. Devices are fabricated in heavily n-doped SOI material using electron beam lithography, with thermal oxidation to reduce the as-defined fin width. Effective channel dimensions, following oxidation and excluding Si/SiO₂ interface dopant deactivation, are ∼2.4 nm $\times$ 32 nm $\times$ 20 nm. Dopant disorder, fin width variation at the nanometre scale, and quantum confinement effects are considered as mechanisms for the formation of tunnel barriers and QDs, with dopant disorder the most likely reason. Arrhenius plots of I_ds vs. 1/T allow extraction of a potential barrier energy ∼0.2 eV along the fin channel. For 180devices fabricated on four chips, 37% show RT SET-FET operation, ∼3 times higher than the corresponding yield observed in previous work on point-contact silicon SETs.