Top-Gate Indium-Tin-Oxide Power Transistors Featuring High Breakdown Voltage of 156 V

Abstract

In this letter, a top-gate (TG) indium-tin-oxide (ITO) power field-effect transistor (FET) with offset design is reported for the first time and carefully investigated by both simulations and experimental measurements. The electrical field distribution within devices possessing different designs were comprehensively studied by TCAD Sentaurus based simulations, which guide the device fabrication for achieving high breakdown voltage ( ${V} _{\text {BD}}\text {)}$ . The device with $1~\mu $ m source-to-drain distance ( ${L} _{\text {SD}}\text {)}$ not only achieves one of the best ${V} _{\text {BD}}$ values of 156 V among all kinds of oxide semiconductor (OS) FET ever reported, but also demonstrates a Baliga’s figure-of-merit (BFoM) beyond the silicon (Si) limit. An improved specific on-state resistance ( ${R} _{\text {on, {sp}}}\text {)}$ of 0.023 m $\Omega \cdot $ cm ² together with a decent ${V} _{\text {BD}}$ of 14 V can be obtained by scaling down the ${L} _{\text {SD}}$ to 200 nm. Our findings highlight the great potential of ITO FET in future back-end-of-line (BEOL) compatible power applications.