Kai Liu;Chong Wang;Xuefeng Zheng;Xiaohua Ma;Kuo Zhang;Wentao Zhang;Junchun Bai;Ang Li;Yue Hao
{"title":"Ultra-Low Gate Leakage Current and Enhanced Gate Reliability in p-GaN HEMT With AlN/GaN/AlN Double Barriers Cap Layer","authors":"Kai Liu;Chong Wang;Xuefeng Zheng;Xiaohua Ma;Kuo Zhang;Wentao Zhang;Junchun Bai;Ang Li;Yue Hao","doi":"10.1109/LED.2024.3435501","DOIUrl":null,"url":null,"abstract":"In this letter, we proposed a p-GaN HEMT with a double barriers cap layer (DB-HEMT) using an AlN/GaN/AlN/ p-GaN gate stack. Double barriers are formed at the gate/AlN and GaN/AlN interfaces, introducing an additional barrier in the p-GaN layer to suppress the gate leakage current (\n<inline-formula> <tex-math>${I}_{\\text {GS}}\\text {)}$ </tex-math></inline-formula>\n and improve the maximum continuous operating voltage (\n<inline-formula> <tex-math>${V}_{\\text {GS- {ma} {x}}}\\text {)}$ </tex-math></inline-formula>\n. The GaN/AlN barrier not only creates a new obstacle but also mitigates the electric field through the opposite polarized electric fields engendered by heterojunction. Consequently, holes are difficult to acquire sufficient energy to overcome this barrier and inject into the p-GaN layer, thereby greatly suppressing \n<inline-formula> <tex-math>${I}_{\\text {GS}}$ </tex-math></inline-formula>\n. Simultaneously, a notable positive shift in threshold voltage (\n<inline-formula> <tex-math>${V}_{\\text {TH}}\\text {)}$ </tex-math></inline-formula>\n is observed due to the dispersion gate voltage of the AlN layer. As a result, the DB-HEMT achieves an ultra-low \n<inline-formula> <tex-math>${I}_{\\text {GS}}$ </tex-math></inline-formula>\n of \n<inline-formula> <tex-math>$2.74 \\times 10^{-{6}}$ </tex-math></inline-formula>\n mA/mm at \n<inline-formula> <tex-math>${V}_{\\text {GS}} = 9$ </tex-math></inline-formula>\n V, a high \n<inline-formula> <tex-math>${V}_{\\text {GS- {ma} {x}}}$ </tex-math></inline-formula>\n of 8.8 V with a 10-year lifetime of 1% failure and a high \n<inline-formula> <tex-math>${V}_{\\text {TH}}$ </tex-math></inline-formula>\n of 2.88 V, demonstrating immense potential for power switching applications.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":null,"pages":null},"PeriodicalIF":4.1000,"publicationDate":"2024-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Electron Device Letters","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10614184/","RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
In this letter, we proposed a p-GaN HEMT with a double barriers cap layer (DB-HEMT) using an AlN/GaN/AlN/ p-GaN gate stack. Double barriers are formed at the gate/AlN and GaN/AlN interfaces, introducing an additional barrier in the p-GaN layer to suppress the gate leakage current (
${I}_{\text {GS}}\text {)}$
and improve the maximum continuous operating voltage (
${V}_{\text {GS- {ma} {x}}}\text {)}$
. The GaN/AlN barrier not only creates a new obstacle but also mitigates the electric field through the opposite polarized electric fields engendered by heterojunction. Consequently, holes are difficult to acquire sufficient energy to overcome this barrier and inject into the p-GaN layer, thereby greatly suppressing
${I}_{\text {GS}}$
. Simultaneously, a notable positive shift in threshold voltage (
${V}_{\text {TH}}\text {)}$
is observed due to the dispersion gate voltage of the AlN layer. As a result, the DB-HEMT achieves an ultra-low
${I}_{\text {GS}}$
of
$2.74 \times 10^{-{6}}$
mA/mm at
${V}_{\text {GS}} = 9$
V, a high
${V}_{\text {GS- {ma} {x}}}$
of 8.8 V with a 10-year lifetime of 1% failure and a high
${V}_{\text {TH}}$
of 2.88 V, demonstrating immense potential for power switching applications.
期刊介绍:
IEEE Electron Device Letters publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects, involving insulators, metals, organic materials, micro-plasmas, semiconductors, quantum-effect structures, vacuum devices, and emerging materials with applications in bioelectronics, biomedical electronics, computation, communications, displays, microelectromechanics, imaging, micro-actuators, nanoelectronics, optoelectronics, photovoltaics, power ICs and micro-sensors.