A High-Speed Dynamic Element Matching Decoder With Integrated Background Calibration Control

IF 2.8 2区工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-07-30 DOI:10.1109/TVLSI.2024.3432640

Tobias Schirmer;Simon Buhr;Felix Burkhardt;Florian Protze;Frank Ellinger

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Abstract

A dynamic element matching (DEM) decoder with integrated mismatch calibration control for high-speed current-steering digital-to-analog converters (CS-DACs) and CSDAC- based direct digital frequency synthesizers (DDFSs) is studied and presented. The DEM algorithm achieves very good averaging of mismatch-induced errors in the succeeding CS-DAC. It features a minimum element transition rate, therefore opimizing the power dissipation and ensuring minimal glitch energy at the output. Due to the chosen network-based architecture, with only a few modifications of the hardware, the decoder allows the integration of a comprehensive current source mismatch calibration that can be fully operated in the background and even in parallel to the regular DEM operation. A proof-ofconcept hardware implementation of the presented decoder was fabricated in a 22-nm FD-SOI CMOS process and characterized in a high-speed DDFS system with a sampling rate of 5 GHz. Measurements reveal a significant improvement in the spurious free dynamic range (SFDR) and signal-to-noise-and-distortion ratio (SNDR) when the calibration and DEM are enabled. Compared to the state-of-the-art (SoA), the presented DDFS achieves one of the best figures of merit.

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集成背景校准控制的高速动态元素匹配解码器

针对高速电流转向数模转换器（CS-DAC）和基于 CSDAC 的直接数字频率合成器（DDFS），研究并提出了一种集成了失配校准控制的动态元素匹配（DEM）解码器。DEM 算法能很好地平均后继 CS-DAC 中失配引起的误差。该算法具有最小的元件转换率，因此可以最大限度地降低功耗，并确保输出端的闪烁能量最小。由于选择了基于网络的架构，只需对硬件进行少量修改，解码器就能集成全面的电流源失配校准功能，该功能可在后台完全运行，甚至与常规 DEM 运行并行。所介绍解码器的概念验证硬件实现采用 22 纳米 FD-SOI CMOS 工艺制造，并在采样率为 5 GHz 的高速 DDFS 系统中进行了鉴定。测量结果表明，启用校准和 DEM 后，无杂散动态范围 (SFDR) 和信噪比 (SNDR) 有了显著改善。与最新技术（SoA）相比，所提出的 DDFS 达到了最佳性能指标之一。

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来源期刊

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 工程技术-工程：电子与电气

CiteScore

6.40

自引率

7.10%

发文量

187

审稿时长

3.6 months

期刊介绍： The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.

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