{"title":"Four Reduced Precision Redundancy by Approximation (4RPA): Design and Analysis of 4-Module Systems","authors":"Salin Junsangsri;Fabrizio Lombardi","doi":"10.1109/TR.2024.3432098","DOIUrl":null,"url":null,"abstract":"Reduced precision redundancy (RPR) has been widely used as an alternative to triple modular redundancy to enhance reliable computing with tolerance to errors and faults; however, it still has stringent requirements for power and area as well as complex decision hardware. Recent works have focused on reduced precision redundancy by approximation (RPA) to attain lower delay, smaller power dissipation, and smaller area because RPA operates using only logic operations (so no arithmetic unit is involved as decision hardware). The proposed RPA-based designs can tolerate up to two erroneous modules, so adding a further data word to the decision process compared to previous three-module based RPA designs found in the technical literature. The proposed designs consist of four modules, two exact data words and two approximate data words (denoted as 2E2A), where E (A) stands for exact (approximate) data words. The probability of generating an output exact data word by RPA under one and both data parts of erroneous modules is analytically found; simulation results are also provided. The difference between simulated and analytical probabilities is at most 7.3%. Figures of merits (such as delay, power dissipation, and area) of the proposed designs are assessed by simulation and compared with RPR and the three-module RPA. The proposed designs incur a similar delay as a three-module RPA; power dissipation and area (due to the additional module) can be adjusted by increasing the number of approximate bits while still retaining a two-module error tolerance. This article also presents its application to image processing, and arithmetic (i.e., the addition operation); the results show that the proposed schemes are very efficient.","PeriodicalId":56305,"journal":{"name":"IEEE Transactions on Reliability","volume":"74 2","pages":"2805-2812"},"PeriodicalIF":5.7000,"publicationDate":"2024-07-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Reliability","FirstCategoryId":"94","ListUrlMain":"https://ieeexplore.ieee.org/document/10617808/","RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q1","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
引用次数: 0
Abstract
Reduced precision redundancy (RPR) has been widely used as an alternative to triple modular redundancy to enhance reliable computing with tolerance to errors and faults; however, it still has stringent requirements for power and area as well as complex decision hardware. Recent works have focused on reduced precision redundancy by approximation (RPA) to attain lower delay, smaller power dissipation, and smaller area because RPA operates using only logic operations (so no arithmetic unit is involved as decision hardware). The proposed RPA-based designs can tolerate up to two erroneous modules, so adding a further data word to the decision process compared to previous three-module based RPA designs found in the technical literature. The proposed designs consist of four modules, two exact data words and two approximate data words (denoted as 2E2A), where E (A) stands for exact (approximate) data words. The probability of generating an output exact data word by RPA under one and both data parts of erroneous modules is analytically found; simulation results are also provided. The difference between simulated and analytical probabilities is at most 7.3%. Figures of merits (such as delay, power dissipation, and area) of the proposed designs are assessed by simulation and compared with RPR and the three-module RPA. The proposed designs incur a similar delay as a three-module RPA; power dissipation and area (due to the additional module) can be adjusted by increasing the number of approximate bits while still retaining a two-module error tolerance. This article also presents its application to image processing, and arithmetic (i.e., the addition operation); the results show that the proposed schemes are very efficient.
期刊介绍:
IEEE Transactions on Reliability is a refereed journal for the reliability and allied disciplines including, but not limited to, maintainability, physics of failure, life testing, prognostics, design and manufacture for reliability, reliability for systems of systems, network availability, mission success, warranty, safety, and various measures of effectiveness. Topics eligible for publication range from hardware to software, from materials to systems, from consumer and industrial devices to manufacturing plants, from individual items to networks, from techniques for making things better to ways of predicting and measuring behavior in the field. As an engineering subject that supports new and existing technologies, we constantly expand into new areas of the assurance sciences.