Digital Circuit Design for the Square Root Computation by Means of Unfolding Techniques

Abstract

Two fixed-point (FP) square root designs based on a bit-by-bit nonrestoring algorithm are unfolded, and compared to an FP pipelined design based on the same algorithm. One of them is unfolded from a bit-serial design, while the other design is unfolded from a smaller version of the pipelined design that has a digit size of 2, for this reason, it is cataloged as “unfolding based.” Hardware utilization is estimated with the theoretical use in the RTL designs and the synthesis report as an auxiliary tool. Results show that the unfolding-based design is comparable and even surpasses the pipelined design when it comes to outputting a first result, being 19.47% faster and using 32.59% of memory of the pipelined design.