Shai Bonen;Suyash Pati Tripathi;Julie McIntosh;Thomas Jager;Sorin P. Voinigescu
{"title":"Investigation of p- and n-Type Quantum Dot Arrays Manufactured in 22-nm FDSOI CMOS at 2–4 K and 300 K","authors":"Shai Bonen;Suyash Pati Tripathi;Julie McIntosh;Thomas Jager;Sorin P. Voinigescu","doi":"10.1109/LED.2024.3435380","DOIUrl":null,"url":null,"abstract":"Large arrays of 1024 single and 2048 coupled quantum dots (QDs) are characterized at 2–4 K and 300 K for the first time using transport measurements. We demonstrate < 0.2 fA gate leakage current, tunnel current transport through 19 series-connected \n<italic>p</i>\n- and \n<italic>n</i>\n-type QDs, 2D-coupling in arrays of 18nm\n<inline-formula> <tex-math>$ \\times 15$ </tex-math></inline-formula>\nnm\n<inline-formula> <tex-math>$ \\times 6$ </tex-math></inline-formula>\nnm QDs with 40-nm spacing, back gate selectivity and tuneability of quantum features, and scaling of the gate-voltage difference between Coulomb peaks with increasing gate oxide thickness and decreasing QD size for both \n<italic>p</i>\n- and \n<italic>n</i>\n-type structures.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":null,"pages":null},"PeriodicalIF":4.1000,"publicationDate":"2024-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10614203","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Electron Device Letters","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10614203/","RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
Large arrays of 1024 single and 2048 coupled quantum dots (QDs) are characterized at 2–4 K and 300 K for the first time using transport measurements. We demonstrate < 0.2 fA gate leakage current, tunnel current transport through 19 series-connected
p
- and
n
-type QDs, 2D-coupling in arrays of 18nm
$ \times 15$
nm
$ \times 6$
nm QDs with 40-nm spacing, back gate selectivity and tuneability of quantum features, and scaling of the gate-voltage difference between Coulomb peaks with increasing gate oxide thickness and decreasing QD size for both
p
- and
n
-type structures.
期刊介绍:
IEEE Electron Device Letters publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects, involving insulators, metals, organic materials, micro-plasmas, semiconductors, quantum-effect structures, vacuum devices, and emerging materials with applications in bioelectronics, biomedical electronics, computation, communications, displays, microelectromechanics, imaging, micro-actuators, nanoelectronics, optoelectronics, photovoltaics, power ICs and micro-sensors.