David G. Refaldi;Gerardo Malavena;Luca Chiavarone;Alessandro S. Spinelli;Christian Monzio Compagnoni
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引用次数: 0
Abstract
In this letter, through experimental evidence collected at room temperature and in the deep-cryogenic regime, we demonstrate that the so-called vertical charge loss from the gate stack of 3-D charge-trap NAND Flash memories is a process featuring widely distributed time constants. Results reveal that the turn-on of these time constants depends on the temperature at which the program operation is carried out. This, combined with the dependence of the time constants on the temperature at which vertical charge loss is monitored, gives rise to an apparent activation energy of the cell threshold-voltage transient during data retention that is close to zero when data retention and program occur at the same temperature. This phenomenology must be carefully taken into account when trying to extend the working temperature of NAND Flash memories down to the deep-cryogenic regime.
期刊介绍:
IEEE Electron Device Letters publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects, involving insulators, metals, organic materials, micro-plasmas, semiconductors, quantum-effect structures, vacuum devices, and emerging materials with applications in bioelectronics, biomedical electronics, computation, communications, displays, microelectromechanics, imaging, micro-actuators, nanoelectronics, optoelectronics, photovoltaics, power ICs and micro-sensors.