RF Performance Augmentation Using DG-InAlN/GaN HEMT

Abstract

The work presented in this study examines the behavior of InAlN/GaN high electron mobility transistor (HEMT) by scaling down the device geometry, including the gate length and barrier thickness, at various operating temperatures. Extensive simulation has been performed using Silvaco’s Victory TCAD simulator tool to analyze the dc and RF performance of InAlN HEMT in terms of ${I}_{\text {on}}/{I}_{\text {off}}$ , intrinsic gain, DIBL, and cutoff frequency. To strengthen the RF performance at increased device length, dual gate (DG) architecture [i.e., Gate 1 (G1) and Gate 2 (G2)] has been adopted, and different gate biasing combinations have been used to investigate the device performance. A tradeoff among intrinsic gain and cutoff frequency is noted from the results. An increment in the cutoff frequency of nearly 57% has been obtained with the introduction of DG along with a deterioration in intrinsic gain.