Pub Date : 2026-01-30DOI: 10.1109/TED.2026.3654316
{"title":"IEEE Transactions on Electron Devices Information for Authors","authors":"","doi":"10.1109/TED.2026.3654316","DOIUrl":"https://doi.org/10.1109/TED.2026.3654316","url":null,"abstract":"","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"73 2","pages":"C3-C3"},"PeriodicalIF":3.2,"publicationDate":"2026-01-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11369827","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146082187","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this work, we demonstrate an innovative dynamic random access memory (DRAM) cell design featuring a vertical junctionless pillar access transistor with a high work-function (WF) molybdenum nitride (MoN) metal gate, enabling enhanced performance and efficiency. By depositing MoN over the gate dielectric at temperatures below $600~^{circ}$ C, we achieved a wrapped-gate transistor array with significantly improved electrical characteristics. Compared to conventional titanium nitride (TiN) gates, the MoN gate exhibits a 0.22-V positive shift in flat-band voltage (VFB) to −0.38 V and a 35% increase in threshold voltage (${V}_{text {th}}text {)}$ to 0.35 V while maintaining identical on-state current (7.6 $boldsymbol {mu }$ A/cell) and subthreshold swing (SS) (82.3 mV/dec). These advancements address critical challenges in DRAM scaling, including leakage reduction and noise immunity, without compromising device performance. The MoN gate’s superior WF ($boldsymbol {Phi }_{text {m}}text {)}$ enables enhanced depletion in the n-type doped channel, ensuring stable operation at 3.3 V with a projected lifetime exceeding ten years. This study establishes MoN as a promising gate material for high-performance vertical junctionless pillar transistors, offering a scalable solution for next-generation 1T1C DRAM architectures.
在这项工作中，我们展示了一种创新的动态随机存取存储器（DRAM）单元设计，其特点是具有高工作功能（WF）氮化钼（MoN）金属栅极的垂直无结柱存取晶体管，从而提高了性能和效率。通过在低于$600~^{circ}$ C的温度下将MoN沉积在栅极电介质上，我们实现了具有显着改善电气特性的封装栅极晶体管阵列。与传统的氮化钛（TiN）栅极相比，MoN栅极的平带电压（VFB）为- 0.38 V，正位移为0.22 V% increase in threshold voltage ( ${V}_{text {th}}text {)}$ to 0.35 V while maintaining identical on-state current (7.6 $boldsymbol {mu }$ A/cell) and subthreshold swing (SS) (82.3 mV/dec). These advancements address critical challenges in DRAM scaling, including leakage reduction and noise immunity, without compromising device performance. The MoN gate’s superior WF ( $boldsymbol {Phi }_{text {m}}text {)}$ enables enhanced depletion in the n-type doped channel, ensuring stable operation at 3.3 V with a projected lifetime exceeding ten years. This study establishes MoN as a promising gate material for high-performance vertical junctionless pillar transistors, offering a scalable solution for next-generation 1T1C DRAM architectures.
{"title":"Innovative DRAM Cell Featuring a Vertical Junctionless Pillar Access Transistor With a High Work-Function Molybdenum Nitride Metal Gate for Enhanced Performance and Efficiency","authors":"Deyuan Xiao;Yi Jiang;Yunsong Qiu;Yuhong Zheng;Daohuan Feng;Chen Yang;Minrui Hu;Guoming Huang;Qinghua Han;Xiang Liu;Kai Shao;Jianfeng Xiao;Jian Chu;Di Ma;Dongsheng Xie;Jinying Liu;Tingting Gu;Xian Zou;Xu Peng;Meng Hao;Zengchao Song;Chao Zhao;Alex See;Kanyu Cao","doi":"10.1109/TED.2025.3638315","DOIUrl":"https://doi.org/10.1109/TED.2025.3638315","url":null,"abstract":"In this work, we demonstrate an innovative dynamic random access memory (DRAM) cell design featuring a vertical junctionless pillar access transistor with a high work-function (WF) molybdenum nitride (MoN) metal gate, enabling enhanced performance and efficiency. By depositing MoN over the gate dielectric at temperatures below <inline-formula> <tex-math>$600~^{circ}$ </tex-math></inline-formula>C, we achieved a wrapped-gate transistor array with significantly improved electrical characteristics. Compared to conventional titanium nitride (TiN) gates, the MoN gate exhibits a 0.22-V positive shift in flat-band voltage (VFB) to −0.38 V and a 35% increase in threshold voltage (<inline-formula> <tex-math>${V}_{text {th}}text {)}$ </tex-math></inline-formula> to 0.35 V while maintaining identical <sc>on</small>-state current (7.6 <inline-formula> <tex-math>$boldsymbol {mu }$ </tex-math></inline-formula>A/cell) and subthreshold swing (SS) (82.3 mV/dec). These advancements address critical challenges in DRAM scaling, including leakage reduction and noise immunity, without compromising device performance. The MoN gate’s superior WF (<inline-formula> <tex-math>$boldsymbol {Phi }_{text {m}}text {)}$ </tex-math></inline-formula> enables enhanced depletion in the n-type doped channel, ensuring stable operation at 3.3 V with a projected lifetime exceeding ten years. This study establishes MoN as a promising gate material for high-performance vertical junctionless pillar transistors, offering a scalable solution for next-generation 1T1C DRAM architectures.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"73 2","pages":"1069-1073"},"PeriodicalIF":3.2,"publicationDate":"2026-01-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146082189","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Dual-gate (DG) WSe2 field-effect transistors (FETs) offer superior electrostatic control and scaling potential compared to conventional back-gate (BG) devices, yet their practical implementation remains limited by the challenge of integrating ultrathin, high-quality gate dielectrics without damaging the 2-D channel. This work presents a CMOS-compatible, low-temperature ($100 ^{circ }$ C) plasma-enhanced atomic layer deposition (PE-ALD) strategy employing aluminum nitride (AlN) as an interface-nucleation layer, followed by thermally grown hafnium dioxide (TH-HfO${}_{{2}}text {)}$ , to realize a top-gate dielectric stack with an equivalent oxide thickness (EOT) below 1 nm. Optimizing the AlN deposition power to 100 W yields the smoothest surface, lowest roughness, and best crystallinity, as confirmed by Raman spectroscopy, atomic force microscopy, and X-ray diffraction (XRD). Electrical characterization under DG operation demonstrates excellent gate modulation, reduced hysteresis, and enhanced drive current, with the 100-W condition achieving the highest drain current of $4.66,times, 10^{-{5}}$ A/$mu $ m post-deposition annealing. These results highlight a scalable, low-power pathway for integrating high-performance dielectrics with 2-D semiconductors, enabling future nanoelectronic and optoelectronic applications.
{"title":"Achieving Sub-1 nm EOT and Enhanced Performance in Monolayer WSe2 FETs via Optimized AlN/HfO2 Dielectrics","authors":"Jia-Hao Chih;Yu-Che Huang;Po-Heng Pao;Chao-Hsin Chien","doi":"10.1109/TED.2025.3648338","DOIUrl":"https://doi.org/10.1109/TED.2025.3648338","url":null,"abstract":"Dual-gate (DG) WSe<sub>2</sub> field-effect transistors (FETs) offer superior electrostatic control and scaling potential compared to conventional back-gate (BG) devices, yet their practical implementation remains limited by the challenge of integrating ultrathin, high-quality gate dielectrics without damaging the 2-D channel. This work presents a CMOS-compatible, low-temperature (<inline-formula> <tex-math>$100 ^{circ }$ </tex-math></inline-formula>C) plasma-enhanced atomic layer deposition (PE-ALD) strategy employing aluminum nitride (AlN) as an interface-nucleation layer, followed by thermally grown hafnium dioxide (TH-HfO<inline-formula> <tex-math>${}_{{2}}text {)}$ </tex-math></inline-formula>, to realize a top-gate dielectric stack with an equivalent oxide thickness (EOT) below 1 nm. Optimizing the AlN deposition power to 100 W yields the smoothest surface, lowest roughness, and best crystallinity, as confirmed by Raman spectroscopy, atomic force microscopy, and X-ray diffraction (XRD). Electrical characterization under DG operation demonstrates excellent gate modulation, reduced hysteresis, and enhanced drive current, with the 100-W condition achieving the highest drain current of <inline-formula> <tex-math>$4.66,times, 10^{-{5}}$ </tex-math></inline-formula> A/<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m post-deposition annealing. These results highlight a scalable, low-power pathway for integrating high-performance dielectrics with 2-D semiconductors, enabling future nanoelectronic and optoelectronic applications.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"73 2","pages":"1063-1068"},"PeriodicalIF":3.2,"publicationDate":"2026-01-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146082188","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-01-09DOI: 10.1109/TED.2025.3644260
{"title":"IEEE Transactions on Electron Devices Information for Authors","authors":"","doi":"10.1109/TED.2025.3644260","DOIUrl":"https://doi.org/10.1109/TED.2025.3644260","url":null,"abstract":"","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"73 1","pages":"C3-C3"},"PeriodicalIF":3.2,"publicationDate":"2026-01-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11344062","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145929649","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-01-02DOI: 10.1109/TED.2025.3647409
Qimao Yang;Jing Guo
Self-consistent dissipative quantum transport and ab initio density-functional theory (DFT) simulations are used to assess the performance potential of homochiral carbon nanotube (CNT) van der Waals (vdW) crystal FETs. At a gate length required for the upcoming technology nodes, the CNT vdW crystal FETs have a significant performance advantage over both the silicon and monolayer MoS2 FETs for high-performance transistor applications. The high packing density of the homochiral CNTs in the CNT vdW crystal boosts the current per channel width, and the interaction between CNTs at the vdW distance only has a small impact on the band structure, which maintains high band-structure-limited velocity and light effective mass. The homochiral CNT vdW crystal FET can achieve a predicted on-current of $sim {2700}{,}mu text {A}/mu text {m}$ at an off-current of $sim !{10}^{-2}{,}mu text {A}/mu text {m}$ and a power supply voltage of ${V}_{text {DD}}={0}.{4}{,}text {V}$ at a gate length of ${12}{,}text {nm}$ . As the gate length is further scaled down below ${10}{,}text {nm}$ , the CNT vdW crystal FETs, however, suffer from significantly degraded subthreshold swing and large leakage current due to pronounced quantum tunneling effects, while monolayer MoS2 has a better performance than both the CNT vdW crystal and silicon FETs at a gate length of ${6}{,}text {nm}$ . For RF applications, the CNT vdW crystal FET outperforms both the silicon and monolayer MoS2 FETs in the presence of parasitic capacitance due to its larger carrier velocity and transconductance per channel width.
采用自洽耗散量子输运和从头算密度泛函理论（DFT）模拟来评估同手性碳纳米管（CNT）范德华（vdW）晶体场效应管（fet）的性能潜力。在即将到来的技术节点所需的栅极长度上，碳纳米管vdW晶体fet在高性能晶体管应用中比硅和单层MoS2 fet具有显着的性能优势。单手性碳纳米管在纳米管vdW晶体中的高填充密度提高了每通道宽度的电流，并且在vdW距离上碳纳米管之间的相互作用对能带结构的影响很小，从而保持了高能带结构限制速度和轻有效质量。同手性碳纳米管vdW晶体场效应管可以在关断电流为$sim !{10}^{-2}{,}mu text {A}/mu text {m}$时实现预测导通电流为$sim {2700}{,}mu text {A}/mu text {m}$，在闸长为${12}{,}text {nm}$时实现预测电源电压为${V}_{text {DD}}={0}.{4}{,}text {V}$。当栅极长度进一步缩小到${10}{,}text {nm}$以下时，由于明显的量子隧穿效应，碳纳米管vdW晶体fet的亚阈值摆幅明显下降，漏电流大，而在栅极长度为${6}{,}text {nm}$时，单层MoS2的性能优于碳纳米管vdW晶体和硅fet。对于射频应用，碳纳米管vdW晶体FET在寄生电容存在下优于硅和单层MoS2 FET，因为它具有更大的载流子速度和每通道宽度的跨导性。
{"title":"Performance Assessment of Homochiral Carbon Nanotube van der Waals Crystal Transistors","authors":"Qimao Yang;Jing Guo","doi":"10.1109/TED.2025.3647409","DOIUrl":"https://doi.org/10.1109/TED.2025.3647409","url":null,"abstract":"Self-consistent dissipative quantum transport and ab initio density-functional theory (DFT) simulations are used to assess the performance potential of homochiral carbon nanotube (CNT) van der Waals (vdW) crystal FETs. At a gate length required for the upcoming technology nodes, the CNT vdW crystal FETs have a significant performance advantage over both the silicon and monolayer MoS<sub>2</sub> FETs for high-performance transistor applications. The high packing density of the homochiral CNTs in the CNT vdW crystal boosts the current per channel width, and the interaction between CNTs at the vdW distance only has a small impact on the band structure, which maintains high band-structure-limited velocity and light effective mass. The homochiral CNT vdW crystal FET can achieve a predicted on-current of <inline-formula> <tex-math>$sim {2700}{,}mu text {A}/mu text {m}$ </tex-math></inline-formula> at an off-current of <inline-formula> <tex-math>$sim !{10}^{-2}{,}mu text {A}/mu text {m}$ </tex-math></inline-formula> and a power supply voltage of <inline-formula> <tex-math>${V}_{text {DD}}={0}.{4}{,}text {V}$ </tex-math></inline-formula> at a gate length of <inline-formula> <tex-math>${12}{,}text {nm}$ </tex-math></inline-formula>. As the gate length is further scaled down below <inline-formula> <tex-math>${10}{,}text {nm}$ </tex-math></inline-formula>, the CNT vdW crystal FETs, however, suffer from significantly degraded subthreshold swing and large leakage current due to pronounced quantum tunneling effects, while monolayer MoS<sub>2</sub> has a better performance than both the CNT vdW crystal and silicon FETs at a gate length of <inline-formula> <tex-math>${6}{,}text {nm}$ </tex-math></inline-formula>. For RF applications, the CNT vdW crystal FET outperforms both the silicon and monolayer MoS<sub>2</sub> FETs in the presence of parasitic capacitance due to its larger carrier velocity and transconductance per channel width.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"73 2","pages":"1056-1062"},"PeriodicalIF":3.2,"publicationDate":"2026-01-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146082184","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-30DOI: 10.1109/TED.2025.3646145
Minjae Jeong;Min Seong Kim;Ki Taeg Shin;Wongyun Youn;Hoon Jeong;Hyun Jae Kim
A structural improvement is introduced to the direct current (dc)-type scan driver to address the electrical limitations and long-term bias stress characteristics of oxide thin-film transistors (TFTs). This modification improves output falling speed and reliability. In conventional oxide TFT-based scan drivers, prolonged positive gate bias can cause threshold voltage shifts. By functionally separating the pull-down (PD) and low-level holding (LLH) paths in the conventional dc-type scan driver, the proposed circuit enhances driving capability and reduces the stress duty cycle under continuous positive bias from over 99% to below 1%. The experimental measurements confirm that the falling time is reduced from 2.1 to 1.4 μs. Furthermore, the SmartSPICE simulations incorporating threshold voltage shifts predict that after one year of operation, the falling time of a conventional scan driver increases to 9.9 μs, whereas the proposed driver shows a modest increase to 1.9 μs.
{"title":"Highly Reliable Oxide TFT-Based DC-Type Scan Driver With Separated Pull-Down and Holding Functions in Displays","authors":"Minjae Jeong;Min Seong Kim;Ki Taeg Shin;Wongyun Youn;Hoon Jeong;Hyun Jae Kim","doi":"10.1109/TED.2025.3646145","DOIUrl":"https://doi.org/10.1109/TED.2025.3646145","url":null,"abstract":"A structural improvement is introduced to the direct current (dc)-type scan driver to address the electrical limitations and long-term bias stress characteristics of oxide thin-film transistors (TFTs). This modification improves output falling speed and reliability. In conventional oxide TFT-based scan drivers, prolonged positive gate bias can cause threshold voltage shifts. By functionally separating the pull-down (PD) and low-level holding (LLH) paths in the conventional dc-type scan driver, the proposed circuit enhances driving capability and reduces the stress duty cycle under continuous positive bias from over 99% to below 1%. The experimental measurements confirm that the falling time is reduced from 2.1 to 1.4 μs. Furthermore, the SmartSPICE simulations incorporating threshold voltage shifts predict that after one year of operation, the falling time of a conventional scan driver increases to 9.9 μs, whereas the proposed driver shows a modest increase to 1.9 μs.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"73 2","pages":"1074-1078"},"PeriodicalIF":3.2,"publicationDate":"2025-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146082186","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This brief presents a system for high-efficiency S-band magnetron microwave power combining based on the mutual synchronization mechanism (peer-to-peer locking mechanism) between magnetrons, which effectively addresses the issues of low efficiency and complex architecture in the existing magnetron microwave combining systems. The system is simplified through a modification of the H–T waveguide tee by introducing multiple tuning pins to control the coupling coefficient precisely. This modification achieves tunable coupling strength and mutual frequency pulling and locking. It leverages the intrinsic coupling characteristics of microwave signals between magnetrons and ensures stable interlocking. Moreover, it significantly simplifies the combining system and eliminates the need for circulators or phase shifters. Additionally, a fixed-length (or tunable) straight waveguide is added to fine-tune the phase difference between the two magnetrons, thereby maximizing the combining efficiency to approximately 99% in experiments. The high combining efficiency is maintained once the combining system is established. The combining efficiency remains above 95% even when different magnetrons are alternated. These results highlight its potential as a high-efficiency solution for magnetron microwave combining applications and industrial-scale use.
{"title":"A High-Efficiency Microwave Power Combining System Based on a Tuned H–T Waveguide Tee","authors":"Dayang Wang;Jianlong Liu;Kongyi Hu;Zhijianmucuo Dong;Zheng Yang;Feifan Ma;Zhong Wang;Baoqing Zeng","doi":"10.1109/TED.2025.3643405","DOIUrl":"https://doi.org/10.1109/TED.2025.3643405","url":null,"abstract":"This brief presents a system for high-efficiency S-band magnetron microwave power combining based on the mutual synchronization mechanism (peer-to-peer locking mechanism) between magnetrons, which effectively addresses the issues of low efficiency and complex architecture in the existing magnetron microwave combining systems. The system is simplified through a modification of the H–T waveguide tee by introducing multiple tuning pins to control the coupling coefficient precisely. This modification achieves tunable coupling strength and mutual frequency pulling and locking. It leverages the intrinsic coupling characteristics of microwave signals between magnetrons and ensures stable interlocking. Moreover, it significantly simplifies the combining system and eliminates the need for circulators or phase shifters. Additionally, a fixed-length (or tunable) straight waveguide is added to fine-tune the phase difference between the two magnetrons, thereby maximizing the combining efficiency to approximately 99% in experiments. The high combining efficiency is maintained once the combining system is established. The combining efficiency remains above 95% even when different magnetrons are alternated. These results highlight its potential as a high-efficiency solution for magnetron microwave combining applications and industrial-scale use.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"73 2","pages":"1079-1082"},"PeriodicalIF":3.2,"publicationDate":"2025-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146082185","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-11DOI: 10.1109/TED.2025.3637350
{"title":"Call for Papers for a Special Issue of IEEE Transactions on Electron Devices: Ultrawide Band Gap Semiconductor Devices for RF, Power and Optoelectronic Applications","authors":"","doi":"10.1109/TED.2025.3637350","DOIUrl":"https://doi.org/10.1109/TED.2025.3637350","url":null,"abstract":"","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 12","pages":"7192-7193"},"PeriodicalIF":3.2,"publicationDate":"2025-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11298382","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145719147","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-11DOI: 10.1109/TED.2025.3637352
{"title":"IEEE Transactions on Electron Devices Information for Authors","authors":"","doi":"10.1109/TED.2025.3637352","DOIUrl":"https://doi.org/10.1109/TED.2025.3637352","url":null,"abstract":"","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 12","pages":"C3-C3"},"PeriodicalIF":3.2,"publicationDate":"2025-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11298381","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145719152","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-02DOI: 10.1109/TED.2025.3630613
Alberto Ferraris;Eunjung Cha;Antonis Olziersky;Marilyne Sousa;Hung-Chi Han;Edoardo Charbon;Kirsten Moselund;Cezar Zota
This work investigates the impact of size scaling on the performance of cryogenic InxGa1_xAs/InP high electron mobility transistors (HEMTs) for low-noise and high-frequency applications. Two quantum-well heterostructures, with 75% and 80% indium content, are examined from 300 to 4 K, including devices with gate lengths down to 40 nm and gate widths down to 380 nm. At cryogenic temperatures, the 80% indium channel achieves a record combination of high-frequency metrics ${textit{f}}_{textit{T}} ={text{622}}$ GHz, ${textit{f}}_{text {MAX}} ={text{733}}$ GHz, and low-noise indication factor $({textit{I}}_{textit{D}})^{textsf{1/2}} / {textit{g}}_{textit{m}} = {text{0}}.{text{17}}~({text{V}}cdot text {mm}/text {S})^{textsf{1/2}}$ on the same device. This performance is enabled by heterostructure engineering, resulting in ultralow ${textit{R}}_{text {ON}} = ~Omega cdot $ $mu $ m. The 75% indium heterostructure instead demonstrates superior low-noise operation, with a minimum subthreshold swing SS = 8.5 mV/decade and a noise indication factor as low as $({textit{I}}_{textit{D}})^{textsf{1/2}} / {textit{g}}_{textit{m}} = {textsf{0.15}}~({text{V}}cdot text {mm}/text {S})^{1/2}$ at optimal device dimensions. These results highlight the potential of InGaAs/InP HEMTs in cryogenic low-noise amplifiers (LNAs), for qubit readout in future high-density quantum computing architectures.
这项工作研究了尺寸缩放对低温InxGa1＿xAs/InP高电子迁移率晶体管（hemt）性能的影响，用于低噪声和高频应用。两个量子阱异质结构，有75% and 80% indium content, are examined from 300 to 4 K, including devices with gate lengths down to 40 nm and gate widths down to 380 nm. At cryogenic temperatures, the 80% indium channel achieves a record combination of high-frequency metrics ${textit{f}}_{textit{T}} ={text{622}}$ GHz, ${textit{f}}_{text {MAX}} ={text{733}}$ GHz, and low-noise indication factor $({textit{I}}_{textit{D}})^{textsf{1/2}} / {textit{g}}_{textit{m}} = {text{0}}.{text{17}}~({text{V}}cdot text {mm}/text {S})^{textsf{1/2}}$ on the same device. This performance is enabled by heterostructure engineering, resulting in ultralow ${textit{R}}_{text {ON}} = ~Omega cdot $ $mu $ m. The 75% indium heterostructure instead demonstrates superior low-noise operation, with a minimum subthreshold swing SS = 8.5 mV/decade and a noise indication factor as low as $({textit{I}}_{textit{D}})^{textsf{1/2}} / {textit{g}}_{textit{m}} = {textsf{0.15}}~({text{V}}cdot text {mm}/text {S})^{1/2}$ at optimal device dimensions. These results highlight the potential of InGaAs/InP HEMTs in cryogenic low-noise amplifiers (LNAs), for qubit readout in future high-density quantum computing architectures.
{"title":"Impact of Size Scaling in Cryogenic InGaAs/InP HEMTs for Low-Noise and High-Frequency Performance","authors":"Alberto Ferraris;Eunjung Cha;Antonis Olziersky;Marilyne Sousa;Hung-Chi Han;Edoardo Charbon;Kirsten Moselund;Cezar Zota","doi":"10.1109/TED.2025.3630613","DOIUrl":"https://doi.org/10.1109/TED.2025.3630613","url":null,"abstract":"This work investigates the impact of size scaling on the performance of cryogenic In<italic><sub>x</sub></i>Ga<sub>1</sub>_<sub>x</sub>As/InP high electron mobility transistors (HEMTs) for low-noise and high-frequency applications. Two quantum-well heterostructures, with 75% and 80% indium content, are examined from 300 to 4 K, including devices with gate lengths down to 40 nm and gate widths down to 380 nm. At cryogenic temperatures, the 80% indium channel achieves a record combination of high-frequency metrics <inline-formula> <tex-math>${textit{f}}_{textit{T}} ={text{622}}$ </tex-math></inline-formula> GHz, <inline-formula> <tex-math>${textit{f}}_{text {MAX}} ={text{733}}$ </tex-math></inline-formula> GHz, and low-noise indication factor <inline-formula> <tex-math>$({textit{I}}_{textit{D}})^{textsf{1/2}} / {textit{g}}_{textit{m}} = {text{0}}.{text{17}}~({text{V}}cdot text {mm}/text {S})^{textsf{1/2}}$ </tex-math></inline-formula> on the same device. This performance is enabled by heterostructure engineering, resulting in ultralow <inline-formula> <tex-math>${textit{R}}_{text {ON}} = ~Omega cdot $ </tex-math></inline-formula><inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m. The 75% indium heterostructure instead demonstrates superior low-noise operation, with a minimum subthreshold swing SS = 8.5 mV/decade and a noise indication factor as low as <inline-formula> <tex-math>$({textit{I}}_{textit{D}})^{textsf{1/2}} / {textit{g}}_{textit{m}} = {textsf{0.15}}~({text{V}}cdot text {mm}/text {S})^{1/2}$ </tex-math></inline-formula> at optimal device dimensions. These results highlight the potential of InGaAs/InP HEMTs in cryogenic low-noise amplifiers (LNAs), for qubit readout in future high-density quantum computing architectures.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 12","pages":"7175-7181"},"PeriodicalIF":3.2,"publicationDate":"2025-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145719127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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