{"title":"Ge n-Channel Hybrid Memory Based on Ferroelectric Charge Trapping Layer With Low Operating Voltage, Large Memory Window, and Negligible Read Latency","authors":"Yi-Fan Chen;Kai-Yang Huang;Chun-Yi Kuo;Yung-Hsien Wu","doi":"10.1109/LED.2024.3437186","DOIUrl":null,"url":null,"abstract":"Ge n-channel hybrid memory based on GeO\n<sub>2</sub>\n/Al\n<sub>2</sub>\nO\n<sub>3</sub>\n tunnel oxide and HfZrO\n<sub>x</sub>\n (HZO) ferroelectric charge trapping layer without block oxide was proposed. The hybrid memory shows promising performance in terms of a large memory window of 2.2 V by applying 5 V/-3 V for \n<inline-formula> <tex-math>$1~\\mu $ </tex-math></inline-formula>\ns, long retention up to 10 years, and robust endurance up to \n<inline-formula> <tex-math>$10^{{7}}$ </tex-math></inline-formula>\n cycles with negligible read latency. It outstands flash memory in terms of higher speed/lower operating voltage due to the ferroelectricity enhanced electric-field across the tunnel oxide while assisting retention of the trapped electrons by dipoles without using block oxide. It also has the competitive advantage over FeFET memory in terms of greatly improved read latency. Besides the integrated merits, the hybrid memory realizes multi-level cell (MLC) and synaptic behaviors such as excitatory/inhibitory postsynaptic currents (EPSC/IPSC), making it eligible in memory-driven neuromorphic computing.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"45 10","pages":"1784-1787"},"PeriodicalIF":4.5000,"publicationDate":"2024-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10620262","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Electron Device Letters","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10620262/","RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
Ge n-channel hybrid memory based on GeO
2
/Al
2
O
3
tunnel oxide and HfZrO
x
(HZO) ferroelectric charge trapping layer without block oxide was proposed. The hybrid memory shows promising performance in terms of a large memory window of 2.2 V by applying 5 V/-3 V for
$1~\mu $
s, long retention up to 10 years, and robust endurance up to
$10^{{7}}$
cycles with negligible read latency. It outstands flash memory in terms of higher speed/lower operating voltage due to the ferroelectricity enhanced electric-field across the tunnel oxide while assisting retention of the trapped electrons by dipoles without using block oxide. It also has the competitive advantage over FeFET memory in terms of greatly improved read latency. Besides the integrated merits, the hybrid memory realizes multi-level cell (MLC) and synaptic behaviors such as excitatory/inhibitory postsynaptic currents (EPSC/IPSC), making it eligible in memory-driven neuromorphic computing.
期刊介绍:
IEEE Electron Device Letters publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects, involving insulators, metals, organic materials, micro-plasmas, semiconductors, quantum-effect structures, vacuum devices, and emerging materials with applications in bioelectronics, biomedical electronics, computation, communications, displays, microelectromechanics, imaging, micro-actuators, nanoelectronics, optoelectronics, photovoltaics, power ICs and micro-sensors.