Material Choices for Tunnel Dielectric Layer and Gate Blocking Layer for Ferroelectric NAND Applications

Abstract

We present an experimental study to compare the impacts of different dielectric materials - Al ₂ O ₃ and SiO ₂ used as the tunnel dielectric layer (TDL) and the gate blocking layer (GBL) on the performance of ferroelectric gate stacks for NAND storage applications. We considered the maximum memory window (MW) and the incremental step program pulse (ISPP) slope as the key performance metrics. In a gate stack with TDL, Al ₂ O ₃ gives higher MW and ISPP performance than SiO ₂ . However, in the GBL gate stack, SiO ₂ has a higher MW and ISPP slope than Al ₂ O ₃ . With SiO ₂ GBL, a maximum MW window of 8.3V was achieved, enabling quad-level cell (QLC) capability. We show that for a similar thickness, SiO ₂ as GBL has the better MW performance, and Al ₂ O ₃ as TDL has a better ISPP performance. This study shows that TDL and GBL with appropriate dielectric material can be used as tuning knobs to achieve the desired ISPP and MW performance for ferroelectric NAND applications.