Process-Variation-Aware In-Memory Computation With Improved Linearity Using On-Chip Configurable Current-Steering Thermometric DAC

Abstract

The in-memory computation (IMC) is a potential technique to improve the speed and energy efficiency of data-intensive designs. However, the scalability of IMC to large systems is hindered by the non-linearities of analog multiply-and-accumulate (MAC) operations and process variation, which impacts the precision of high bit-width MAC operations. In this paper, we present an IMC architecture that is capable of performing multi-bit MAC operations with improved speed, linearity, and computational accuracy. To improve the speed/linearity of the IMC-MAC operations, the image and weight data are applied by using the pulse amplitude modulation (PAM) and thermometric techniques, respectively. Although the PAM technique improves the speed of the IMC-MAC operations, it has linearity issues that need to be addressed. Based on the detailed linearity analysis of the IMC-MAC circuit, we proposed two approaches to improve the linearity and the signal margin (SM) of the IMC architecture. The proposed configurable current steering thermometric digital-to-analog converter (CST-DAC) array is employed to provide the PAM signals with various dynamic ranges and non-linear gaps that are required to improve the linearity/SM. The proposed combined PAM and thermometric IMC (PT-IMC) architecture is designed and fabricated in the TSMC 180-nm CMOS process. The post-silicon calibration of the design point mitigates the process-variation issues and provides the maximum SM (close to the simulation results). Furthermore, the proposed PT-IMC architecture performs MNIST/CIFAR-10 data set classification with an accuracy of 98%/88%. In addition, the PT-IMC architecture achieves a peak throughput of 12.41 GOPS, a normalized energy efficiency of 30.64 TOPS/W, a normalized figure-of-merit (FOM) of 3039, a loss in the SM of 8.3% with respect to the ideal SM, and a computational error of 0.41%.