LiCryptor: High-Speed and Compact Multi-Grained Reconfigurable Accelerator for Lightweight Cryptography

IF 5.2 1区 工程技术 Q1 ENGINEERING, ELECTRICAL & ELECTRONIC IEEE Transactions on Circuits and Systems I: Regular Papers Pub Date : 2024-08-01 DOI:10.1109/TCSI.2024.3434686
Hoai Luan Pham;Vu Trung Duong Le;Van Duy Tran;Tuan Hai Vu;Yasuhiko Nakashima
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Abstract

Emerging modern internet-of-things (IoT) systems require hardware development to support multiple 8/32/64-bit lightweight cryptographic (LWC) algorithms with high speed and energy efficiency to ensure diverse security requirements. Accordingly, a coarse-grained reconfigurable array (CGRA) is considered the most effective architecture for achieving high speed, low power, and high flexibility for implementing LWC algorithms. However, existing CGRA designs for cryptography focus only on improvements to outdated 8/32-bit algorithms, suffer from large area requirements, and have long compilation times. To address these issues, this paper proposes a new CGRA-based accelerator named LiCryptor to support various 8/32/64-bit LWC algorithms with high speed and small area. Three innovative ideas are proposed to enable LiCryptor to achieve these goals: a compact multi-grained processing element array (M-PEA), a shared 8/32/64-bit arithmetic logic unit (ALU), and an assembly-like inline directive (AID) mapping method. The LiCryptor has been successfully implemented and verified on the Xilinx ZCU102 FPGA. Real-time performance evaluation across various LWC algorithms on FPGA shows that LiCryptor is 1.33 to 4 times better in execution time and 3.4 to 153 times better in power-delay products (PDP) compared to today’s most powerful CPUs. Notably, evaluation of AID mapping on the ARM Cortex-A53 CPU of the ZCU102 FPGA shows that its compilation time is less than 1.5 ms for most LWC algorithms, at least 2,333 times faster than CFG mapping in current CGRAs. Moreover, experimental results on 45nm ASIC technology show that the LiCryptor significantly outperforms existing CGRAs and other reconfigurable designs in terms of throughput and area efficiency.
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LiCryptor:用于轻量级密码学的高速紧凑型多粒度可重构加速器
新兴的现代物联网(IoT)系统要求硬件开发能够支持多种 8/32/64 位轻量级加密(LWC)算法,并具有高速度和高能效,以确保不同的安全要求。因此,粗粒度可重构阵列(CGRA)被认为是实现高速、低功耗和高灵活性以实现 LWC 算法的最有效架构。然而,现有的用于密码学的 CGRA 设计仅侧重于改进过时的 8/32 位算法,存在面积要求大、编译时间长等问题。为解决这些问题,本文提出了一种基于 CGRA 的新型加速器 LiCryptor,以高速、小面积支持各种 8/32/64 位 LWC 算法。为使 LiCryptor 实现这些目标,本文提出了三个创新理念:紧凑型多粒度处理元件阵列 (M-PEA)、共享 8/32/64 位算术逻辑单元 (ALU) 和类汇编内联指令 (AID) 映射方法。LiCryptor 已在 Xilinx ZCU102 FPGA 上成功实现并通过验证。在 FPGA 上对各种 LWC 算法进行的实时性能评估显示,与当今最强大的 CPU 相比,LiCryptor 的执行时间缩短了 1.33 到 4 倍,功耗延迟积(PDP)缩短了 3.4 到 153 倍。值得注意的是,在 ZCU102 FPGA 的 ARM Cortex-A53 CPU 上进行的 AID 映射评估表明,对于大多数 LWC 算法,其编译时间小于 1.5 毫秒,比当前 CGRA 中的 CFG 映射至少快 2,333 倍。此外,在 45 纳米 ASIC 技术上的实验结果表明,LiCryptor 在吞吐量和面积效率方面明显优于现有 CGRA 和其他可重构设计。
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来源期刊
IEEE Transactions on Circuits and Systems I: Regular Papers
IEEE Transactions on Circuits and Systems I: Regular Papers 工程技术-工程:电子与电气
CiteScore
9.80
自引率
11.80%
发文量
441
审稿时长
2 months
期刊介绍: TCAS I publishes regular papers in the field specified by the theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing. Included is the whole spectrum from basic scientific theory to industrial applications. The field of interest covered includes: - Circuits: Analog, Digital and Mixed Signal Circuits and Systems - Nonlinear Circuits and Systems, Integrated Sensors, MEMS and Systems on Chip, Nanoscale Circuits and Systems, Optoelectronic - Circuits and Systems, Power Electronics and Systems - Software for Analog-and-Logic Circuits and Systems - Control aspects of Circuits and Systems.
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